RIA: Statistical Design of Analog and Mixed Signal Circuits

随着高速电路和模数混合设计的出现，确保设计不受制造工艺变化的影响变得非常重要。设计必须防止两种类型的故障：灾难性短路和开路，以及参数电路由于参数偏离标称值太远而失效的参数。本文主要研究模拟和混合信号系统的统计仿真。目前正在研究三个问题。首先，采用基于spice的宏建模方法来减少模拟元件的仿真时间。在给定性能需求的情况下，寻找最佳参数的算法。其次，对模拟元件的电路级和宏模型级统计过程模型进行了探索。针对模拟电路制造过程的复杂参数模型，研究人员正在开发最坏情况分析和参数良率计算算法。第三，建立新的突变故障模型是有效计算测试集突变故障覆盖率算法的基础。从这些信息可以计算出模拟元件的突变产率。

With the advent of high speed circuits and mixed analog-digital designs, it is important to make sure designs are insensitive to manufacturing process variations. Designs must protect against two types of faults: catastrophic-short and open circuits, and parametric where circuits fail due to parameters deviating too far from their nominal values. This research is on statistical simulation of analog and mixed signal systems. Three research problems are being pursued. First, a SPICE-based macromodeling approach to reducing the simulation time of analog components is being used. An algorithm for finding the best parameters, given the performance needs is being sought. Second, both circuit level and macromodel level statistical process models for analog components are being explored. Algorithms for worst case analysis and for computing parametric yield, which are attuned to the complex parameter models of the analog circuit manufacturing process are being developed. Third, a new catastrophic fault model is the basis of algorithms for efficiently computing catastrophic fault coverage of test sets. From this information catastrophic yield of analog components can be computed.