RIA: Fast Simulation of Computer Architectures Using Field-Programmable Gate Arrays as Hardware Accelerators

本研究以现场可编程门阵列作为硬件加速器，进行架构级仿真。这项研究的目标包括开发一种既通用又可用于生成快速高效模拟器的体系结构规范范型，开发基于图形用户界面的输入工具，开发用于将体系结构描述自动转换为FPGA编程信息的工具，以及实现跟踪驱动的执行环境来运行模拟。这项工作背后的关键思想是使用FPGA在事件、依赖、资源和延迟级别上模拟门级以上的系统。现场可编程门阵列对硬件实现的数据结构的大小进行了限制，它将通过软件监视器进行扩展，以允许虚拟的、不受长度限制的结构。通过使用适应于高级综合和C程序编译的方法，模拟将从高级描述自动转换。为了帮助输入建筑描述，将开发一个图形用户界面工具。系统描述的范例将基于系统行为的离散事件体系结构模型。该范例将是分层的，并提供一个库，该库利用现有的高速缓存和处理器模拟的快速模拟技术。

This research is on architectural-level simulation using field- programmable gate arrays as hardware accelerators. The goals of this research include the development of a paradigm for architectural specification that is both general-purpose and can be used to produce fast and efficient simulators, development of a graphical user interface-based entry tool, development of tools for automatic translation of an architectural description to FPGA programming information, and implementation of a trace-driven execution environment to run the simulations. The key idea behind this work is to use FPGA's to simulate a system above the gate level, at the level of events, dependencies, resources and delays. FPGA's place a limit on the size of the hardware-implemented data structures, which will be extended via a software monitor to allow virtual, unlimited-length structures. The simulation will be automatically translated from a high-level description by use of methods adapted from high-level synthesis and the compilation of C programs. To aid in entering the architectural description, a graphical user interface tool will be developed. The paradigm for system description will be based on a discrete-event architectural model of system behavior. This paradigm will be hierarchical and provide a library that takes advantage of existing fast simulation techniques for cache and processor simulation.