Research Initiation Award: Reducing the Impact of Synchronization Latency in Shared-Memory Multiprocessors

9410457广告本研究的目的是开发和评估技术，减少共享内存多处理器的同步延迟的影响。 最近的趋势表明，未来的微处理器将采用积极的技术（例如， 多指令发布、动态调度）以利用并行级并行性。 然而，当前的共享内存多处理器通常需要一个处理器在同步读取时停止，直到读取完成，这就排除了未来单处理器的充分利用。 研究了两种减少同步延迟影响的方法：（a）重叠显式同步的延迟，（B）使用隐式同步（在可能的情况下）消除同步延迟。 这项研究的主要组成部分是：（1）基于用于重叠获取操作的保护指令的实用硬件技术，（2）通过使用显式和隐式同步的新组合来减轻隐式同步引起的实现开销，（3）确定程序员可以提供的高级注释形式的信息以增强对解释级并行性的检测，以及（4）使用真实的应用的广泛的预防级模拟对上述技术的功效进行定量评估。 这项研究是一个必要的步骤，使更广泛地接受并行机，因为它将使机器更具有成本效益，更充分地利用下一代微处理器的潜力，并将扩大支持类的应用程序，允许有效执行更细粒度的应用程序。 ***

9410457 Adve The objective of this research is to develop and evaluate techniques for reducing the impact of synchronization latency in shared-memory multiprocessors. Recent trends indicate that future microprocessors will employ aggressive techniques (e.g., multiple instruction issue, dynamic scheduling) to exploit instruction-level parallelism. Current shared-memory multiprocessors, however, usually require a processor to stall on synchronization reads until the read completes, precluding the full exploitation of future uniprocessors. The research studies two approaches for reducing the impact of synchronization latency: (a) overlapping latency of explicit synchronizations, and (b) using implicit synchronization (where possible) to eliminate synchronization latency. The key components of the study will be: (1) a practical hardware technique based on guarded instructions for overlapping acquire operations, (2) alleviating implementation overheads incurred with implicit synchronization by using a novel combination of explicit and implicit synchronization, (3) determining information in the form of high-level annotations that programmers can provide to enhance detection of instruction-level parallelism, and (4) a quantitative evaluation of the efficacy of the above techniques using extensive instruction-level simulations of real applications. This research is a necessary step towards enabling wider acceptance of parallel machines because it will enable machines to be more cost-effective by exploiting more fully the potential of next-generation microprocessors, and will broaden the supported class of applications by allowing the efficient execution of finer-grained applications. ***