An Integrated VHDL-based Synthesis and Verification System for VLSI Systems

本文的研究方向是数字系统的综合与验证。这项工作的计算基础是二进制决策图（BDD）的数据结构和扩展。在低功耗电路设计中，BDD技术的新思想被用于合成算法，并通过电路的概率行为来估计功耗。分解概念，如撕裂，正在研究中，以评估非常大的电路的性质。在验证中，正在研究近似探索思想，以用于检查非常大的电路的等效性。分层验证能力，其中电路的部分在位级建模，其他部分在字级建模，正在进行检查。为了在高级综合和高级验证之间提供良好的联系，以及验证高级VHDL描述，正在探索非确定性系统的精细比较，例如双仿真等效和测试等效以及预订单。

This research is on synthesis and verification of digital systems. The computational basis for the work is the binary decision diagram (BDD) data structure and extensions. In low power circuit design, new ideas in BDD technology are being used for synthesis algorithms, and to estimate power consumption via probablistic behavior of circuits. Decomposition concepts, such as tearing, to assess properties of very large circuits are being investigated. In verification, approximate exploration ideas are being examined for use in checking equivalence of very large circuits. Hierarchical verification capabilities, where parts of the circuit are modeled at the bit level and other parts at the word level, are being examined. To provide a sound connection between high level synthesis and high level verification, as well as to validate high level VHDL descriptions, refined comparisons of non-deterministic systems, such as bi-simulation equivalence and testing equivalence and pre-orders are being explored.