A Study of Long-Term Architectural Limits to Computing: Galileo

伽利略是一项对计算机领域远程技术进步的影响的调查。虽然由于在非常广泛的技术范围内取得了快速的进步，进行范围狭窄的预测是困难和有风险的，但推断当前的趋势并对未来的计算机构件做出明智的猜测是可能的。因此，将当前的发展速度外推到短短十年，这表明令人难以置信的强大计算机系统可能不仅是可能的，甚至是负担得起的。当前的技术趋势无疑将受到新发现和远在达到这样的性能水平之前的限制的影响。这项研究的目标是确定那些可能发生冲突或以其他方式迟缓的发展方向，并调查这些影响的影响。未来的机器无疑将大大降低所有操作的成本，但一些操作将变得比另一些操作更便宜。一个主要目标是确定不同类型的操作的相对改进，并了解这些更改将如何影响体系结构、编程环境和使用的算法。处理器长期以来一直是计算机系统的核心，尽管已经写了很多关于其他限制的文章，但CPU在今天的体系结构中仍然扮演着核心角色。处理器的效率越来越低，限制因素不是它的峰值处理能力，而是系统提供使其忙碌的工作的能力。虽然处理能力正在迅速变得更便宜，但有效使用内存和通信正在成为实现更高性能的关键挑战。二十多年来，内存成本一直在快速而稳定地下降，而且每位成本还将继续下降。然而，访问时间并没有显著改善，高带宽、低延迟的存储器总是相对昂贵的。内存访问瓦片和带宽方面的限制已经构成了困难的设计挑战，而技术趋势只会加剧这一挑战。这项研究正在调查一个系统如何通过在任何可以有效使用的地方应用廉价的处理能力来从其内存系统中获得更高的性能。在某种意义上，该系统成为具有处理能力的存储器模块的集合，其方式是通过最小化存储器模块之间的通信来最大化存储器的有效利用。存储器访问时间和存储器延迟密切相关。两者对于高性能系统都至关重要，而且两者都可以以牺牲另一个为代价进行优化。如今，内存延迟似乎是更紧迫的问题，目前的许多研究都致力于减少或容忍内存延迟。假设这些技术中的一些是成功的，那么更根本的内存带宽问题就会出现。虽然有可能建立任意高带宽的系统，但似乎最重要的新出现的挑战之一是最有效地利用模块之间可用的任何带宽。按照今天的标准，未来的系统将拥有巨大的处理能力、巨大的内存和令人难以置信的通信带宽。计算机系统将受到内存模块容量不足和通信路径带宽有限的限制，处理器将慷慨地分布在需要的地方，以优化内存和通信带宽的效率。伽利略正在研究这种系统的架构应该与今天的系统有何不同。伽利略正在研究这种系统的体系结构应该如何与当今的系统不同，以及这种系统应该如何编程。

Galileo is an investigation into the implications of long range technology advances across the computer field. While projections of narrow scope are difficult and risky because of the rapid progress over a very broad range of technology, it is possible to extrapolate current trends and make intelligent guesses about future computer building blocks. Extrapolating current rates of progress to as little as a decade hence suggesting that incredibly powerful computer systems might not be only possible, but even affordable. Current technology trends will undoubtedly be affected by new discoveries and by limitations long before such performance levels are reached. It is the goal of this research to identify those development directions that are likely to come into conflict or otherwise be retarded, and to investigate the implications of these effects. Future machines will undoubtedly much lower costs of all operations, but some operations will become much cheaper than others. A major goal is to identify the relative improvements on different kinds of operations, and to understand how these changes will affect architecture, the programming environment, and the algorithms used. The processor has long been the heart of a computer system, and though much has been written about other limitations, the CPU still plays a central role in today's architectures. Increasingly the processor is becoming less effective, limited not by its peak processing power, but by the ability of the system to provide work to keep it busy. While processing power is rapidly becoming cheaper, the effective use of memory and communication is becoming the critical challenge in achieving higher performance. Memory costs have declined rapidly and steadily for more than twenty years, and will continue to decline in cost per bit. Access time has not improved dramatically, however, and high-bandwidth, low latency-memory will always be relatively expensive. Limitations in memory access tile and bandwidth are already posing difficult design challenges, and this will only be aggravated by technology trends. This research is investigating how a system can get higher performance form its memory system by applying cheap processing power wherever it can be used effectively. In some sense, the system becomes a collection of memory modules with processing power distributed in ways to maximize the effective use of memory by minimizing communications between memory modules. Memory access time and memory latency are intimately related. Both are critical for a high-performance system, and either can be optimized at the expense of the other. Today memory latency seems to be the more urgent problem, and much current research is devoted to reducing or tolerating memory latency. Assuming that some of these techniques are successful, the more fundamental problem of memory bandwidth emerges. While it may be possible to build systems of arbitrarily high bandwidth, it appears that one of the most important emerging challenges is to make the most effective use of whatever bandwidth is available between modules. By today's standards, future systems will have enormous processing power, huge amounts of memory, and incredible communications bandwidth. Computer systems will be limited by memory modules of insufficient capacity and communication paths of limited bandwidth, with processor distributed generously wherever needed to optimize the effectiveness of memory and communication bandwidth. Galileo is investigating how the architecture of such systems should differ from systems of today. Galileo is investigating how the architecture of such systems should differ from systems of today, and how such systems should be programmed.