CAREER: Optically-Interconnected Fully-Adaptive Network Router

9624251 Pinkston构建通用万亿次计算机系统的先驱是网络技术的进步，以达到更高的性能水平。在多个高性能处理器作为一个连接单元协同工作的并行处理器系统中，性能由处理器节点的有效利用率决定，而处理器节点的有效利用率主要取决于通信效率。并行处理环境中的通信骨干是互连网络。我们建议在混合GaAs/硅芯片中设计和实现一个灵活的完全自适应无死锁光网络路由器，其特征在于一种新的分组路由算法，普遍适用于任何网络拓扑结构。这项研究旨在通过探索基于硬件的解决方案来提高并行处理器的通信效率，从而进一步推动互连网络技术的发展。这项工作充分利用了当前互连网络路由器架构的趋势和光学/光子技术的持续进步。 我们提出的光路由器提供了一个灵活的框架，探索许多设计方案从来没有想象过，由于其高度的资源解耦和拓扑独立性。在路由器的构建中需要研究的有趣问题包括如何准确地检测死锁，如何有效地实现无死锁恢复通道，如何实现低开销的光互连内部和外部流量控制，以及如何集成光发送器，光接收器。和复杂的电子路由器逻辑电路到单个光电子VLSI路由器芯片上。一旦建立路由器，可以进一步理解的有趣的问题包括完全自适应虫洞路由的性能和/或容错优势，误路由能力，使用DB资源不仅从潜在的死锁中恢复，而且还可以缓解正常的网络拥塞，以及使用密集的高带宽光I/O的完全自适应网络路由器。我们将系统地解决这些问题和其他重要问题，因为我们去设计，建造，并与这种新颖的网络路由器进行试验。 这项研究大大增加了光互连/光子交换基础设施。这项工作是开创性的，据我们所知，我们是第一个提出的研究，包括先进的交换，流量控制和路由功能的光互连网络设计。主要研究者将领导一个专门的研究团队，由本科生、研究生组成，研究经验丰富。和研究生合作研究人员。此外，重要的研究成果将在课堂上使用，作为教学中的优秀例证。因此，我们将证明，当前和下一代互连网络技术，如虫洞交换，虚拟通道流，和自适应路由是可行的纳入基于光学的互连网络。这将提供一个平台，在其上构建光学互连的并行处理系统，影响该技术对未来系统的适用性。 ***

9624251 Pinkston The precursor to building general-purpose teraflop computer systems is the advancement of network technology to reach much higher levels of performance. In parallel processor systems, where multiple high performance processors work cooperatively as one connected unit, performance is determined by the effective utilization of processor nodes which, predominately, depends upon communication efficiency. The backbone for communication in parallel processing environments is the interconnection network. We propose to design and implement in a hybrid GaAs/silicon chip a flexible fully-adaptive deadlock-free optical network router featuring a new packet routing algorithm universally applicable to any network topology. This proposed research serves to further advance the state-of-the-art in interconnection network technology by exploring hardware-based solutions for increasing parallel processor communication efficiency. This work leverages ofd of current trends in interconnection network router architecture and continuing advancements in optical/photonic technology. Our proposed optical router provides a flexible framework for exploring many design alternatives never before imagined due to its high degree of resource decoupling and topological independence. Interesting issues to be investigated in the building of the router include how to accurately detect deadlock, how to efficiently implement the deadlockfree recovery lane, how to implement low overhead internal and external flow control for optical interconnects, and how to integrate optical transmitters, optical receivers. and complex electronic router logic circuitry onto a single optoelectronic VLSI router chip. Interesting issues that can be further understood once the router is built include the performance and/or fault tolerance advantages of fully adaptive wormhole routing, misrouting capability, the use of the DB resource for not only recovering from potential deadlocks but also for relieving n ormal network congestion, and the use of dense high bandwidth optical I/O for fully adaptive network routers. We will systematically address these and other important issues as we go about designing, building, and experimenting with this novel network router. This research adds significantly to optical interconnect/photonic switching infrastructure. This work is pioneering in that, to our knowledge, we are the first to propose research that encompasses advanced switching, flow control, and routing functionality in optical interconnection network design. The principal investigator will lead a dedicated research team ranging in research experience consisting of undergraduate, graduate. and post-graduate collaborative researchers. Moreover, important research achievements will find use in the classroom to serve as excellent illustrations in teaching. Hence, we will demonstrate that current and next-generation interconnection network techniques such as wormhole switching, virtual channel flow, and adaptive routing are feasibly incorporated in optically-based interconnection networks. This will provide a platform on which to build optically interconnected parallel processing systems, impacting the applicability of this technology to future systems. ***