Quality vs. Cost Tradeoffs in VLSI Testing: An Empirical Analysis of Sematech Test Data

VLSI制造测试成本的两个重要组成部分是测试长度和废品率。后者是不良设备逃避测试检测的比率。本研究探索一种新的方法来估计拒绝率，使最佳的平衡之间的测试长度和拒绝率可以达到。该方法包括扩展以处理制造商通常采用的多种类型的测试，例如固定、IDDQ、延迟和功能。用于估计拒绝率的分析方法太复杂，无法准确捕获参数之间的所有相互作用，这导致不可靠的拒绝率估计。 在这个项目中，正在开发一个经验性的，但强大的模型。 它基于在测试仪数据中观察到的特性，这些特性被证明对于各种制造技术和测试类型都是不变的。

Two significant components of VLSI manufacturing test cost are the test length, and the reject rate. The latter is the rate at which bad devices escape detection by the test. This research explores a new approach to estimate the reject rate so that optimum balance can be struck between the test length and the reject rate. The approach includes extensions to handle multiple types of tests that are commonly employed by the manufacturers, e.g. stuck-at, IDDQ, delay, and functional. Analytical methods for estimating the reject rate are too complex to capture accurately all interactions among parameters, which leads to unreliable reject rate estimates. In this project an empirical, yet robust model is being developed. It is based on properties observed in tester data that are demonstrated to be invariant for a wide range of manufacturing technologies and types of tests.