A New Query/Request Framework to Develop Tests for Systems- on-Silicon that use IP Cores

包含知识产权（IP）的核被广泛用于片上系统（SOC）的成本有效和及时的设计。这给制造测试带来了问题，因为核心包含专有信息，并且难以开发有效的测试方法。这项研究正在开发一种新的查询/请求（Q/R）模式，使开发测试的SOC没有获得直接访问核心供应商的IP。正在探索用于仿真、故障仿真、测试生成的新程序。这些过程封装关于每个核心的信息，并且仅提供不包含IP的某些类型的信息以响应来自系统级模块的Q/R。一个系统级模块，开发测试整个SOC也正在开发中。在Q/R范式研究下开发的工具包括故障模拟器、测试生成器、可测性设计（DFT）程序和内建自测试（BIST）电路。

Cores containing intellectual property (IP) are being used widely for cost-effective and timely design of systems-on chip (SOC). This presents a problem for manufacturing test in that cores contain proprietary information, and effective test methods are difficult to develop. This research is developing a new Query/Request (Q/R) paradigm to enable development of tests for a SOC without obtaining direct access to the core vendors' IP. New procedures for simulation, fault simulation, test generation are being explored. These procedures encapsulate information about each core, and provide only certain types of information that do not contain IP in response to a Q/R from the system level module. A system level module to develop tests for the entire SOC is also being developed. Tools being developed under the Q/R paradigm research include fault simulators, test generators, procedures for design-for-testability (DFT), and built-in self-test (BIST) circuitry.