New Methods for Exploiting Program Structure and Behavior in Computer Architecture, and their Applications

多媒体处理、数字信号、图像和视觉处理以及科学计算等应用产生的计算任务是结构化和重复性的，表现出不同程度的指令级并行性(ILP)。此外，计算某些函数的需求及其资源需求随着应用程序和时间的不同而不同。该项目的总体目标是开发和使用新的概念，如可重构功能单元(FU)、高速缓冲存储器和可重构总线架构来实现平衡计算，即匹配计算带宽和存储器带宽。研究将解决架构设计中的问题，这些架构允许重新配置资源以使以下架构级参数动态可变：FU的数目和类型、片上寄存器和高速缓冲存储器的数量、片上存储器资源与FU数目的动态交换能力以及这些单元之间的互连。将开发一个具有可重新配置逻辑块的处理器核心，以使该体系结构适应应用程序的计算和内存带宽需求。还将研究和评估将重新配置方案集成到处理器芯片上的片上FU和高速缓存存储器中的效果。将开发和分析ABC(自适应平衡计算)体系结构的高层设计。预计研究成果将显著提高计算效率。

Applications, such as multimedia processing, digital signal, image and vision processing, and scientific computing, generate computation tasks that are structured and repetitive exhibiting varying degree of instruction-level parallelism (ILP). Moreover, the demands to compute certain functions and theirresource needs vary with applications and time. The overall goal of this project is to develop and use novel ideas such as reconfigurable functional units (FUs), cache memory, and reconfigurable bus architectures to achieve balanced computing, i.e. match the computing bandwidth to the memory bandwidth.The research will address issues in designing architectures that allow reconfiguration of resources to make the following architecture level parameters dynamically variable: number and types of FUs, amount of on-chip register and cache memory, an ability to trade the on-chip memory resources with the numberof FUs dynamically, and the interconnectivity between these units. A processor core with reconfigurable logic blocks to make the architecture adaptive to the applications' computing and memory bandwidth needs will be developed. Effects of integrating reconfiguration schemes into the on-chip FUs and cache memorieson a processor chip will also be studied and evaluated. A high-level design for the ABC (Adaptive Balanced Computing) architecture will be developed and analyzed. It is expected that the research results will significantly improve the efficiency of computation.