NSF CNPq Collaborative Research on Design Environments for Application-Specific Programmable Processors

这项研究是关于嵌入式系统设计工具，用于构建定制的特定应用程序指令处理器（ASIP）体系结构，这些体系结构不会更大，也不会比必要的更复杂。开发一个ASIP，不仅需要硬件设计，还需要使用一组评估工具，如汇编器、编译器和模拟器。本研究使用处理器描述作为开发这些工具以及硬件综合的共同起点。麻省理工学院开发的isdl语言正是为了这个目的，被用于开发一个完整的软件开发环境，以及硬件生成。该模拟器用于获取应用程序代码的时钟周期估计，并评估整体体系结构性能。处理器数据路径的合成支持硬件生成，并提供准确的周期时间估计。为了支持软件编译，将开发可目标汇编器、代码生成器和优化器，它们接受ISDL中的机器描述和要编译到所描述的机器上的程序作为输入。正在评估在合理的时间内生成最高质量代码的新优化。我们的可重定向编译器的基础是SPAM，这是一个嵌入式编译器框架，由麻省理工学院、普林斯顿大学和巴西UNICAMP的研究人员开发。在许多情况下，应用程序代码不是用高级编程语言编写的，必须处理汇编或遗留代码。因此，优化二进制到二进制转换的自动方法正在研究中。为了做到这一点，遗留的二进制/汇编代码被反编译成编译器基础设施使用的中间形式，然后使用优化编译器技术为目标体系结构生成高质量的汇编。

This research is on embedded systems design tools for building customapplication-specific instruction processor (ASIP) architectures that are nobigger, or no more complex than necessary. Developing an ASIP, not onlyrequires hardware design, but also requires the use of a set of evaluationtools such as an assembler, compiler and simulator. This investigation usesa processor description to serve as a common starting point for thedevelopment of these tools, as well as for hardware synthesis. The ISDLlanguage, being developed at MIT, for exactly this purpose is being used indeveloping a complete software development environment, as well as hardwaregeneration. The simulator is used to obtain clock cycle estimates onapplication code, and to evaluate the overall architecture performance.Synthesis of processor datapaths enables hardware generation and providesaccurate, cycle-time estimates. To support software compilation, aretargetable assembler, code generator and optimizer will be developed thatreceive as input both a machine description in ISDL, and the program to becompiled onto the described machine. New optimizations to produce code ofthe highest quality in a reasonable amount of time are being evaluated. Thebase of our retargetable compiler is SPAM, an embedded compiler frameworkthat has been developed by researchers at MIT, Princeton and UNICAMP,Brazil. In many cases, application code is not written in high-levelprogramming languages, and it is necessary to deal with assembly or legacycode. Thus automatic methods for optimized binary-to-binary translation arebeing investigated. To do this, the legacy binary/assembly code isdecompiled to intermediate forms used by our compiler infrastructure andthen using the optimizing compiler technology to generate high-qualityassembly for the target architecture.