PECASE: Self-assembly Processes for Practical Nano-scale Electronic Devices and Interconnect

埃德温·C KanECS-9985062本提案的目的是开发用于电子器件和互连的纳米级自组装工艺。 通过集成先进的CMOS技术和自组装工艺，将设计、制造、表征和优化用于逻辑和存储器的新型多元件模块，以实现超越当前光刻极限的功能和性能。 过程开发将集中在影响自组装和奥斯特瓦尔德熟化的物理机制的表面相互作用和扰动。 将实施两个主要组成部分，以促进研究及时渗透到教育中。 由于技术开发的生命周期非常短，这对半导体研究至关重要。 首先，模拟软件的开放式架构将使研究生和本科生能够学习具有完整数值功能的新研究模型，并在同一平台上与其他人交换模块进行比较。其次，新的研究趋势将有助于确定核心课程内容并简化课程系列，以提高学习效率。

Edwin C. KanECS-9985062The purpose of this proposal is to develop the nano-scale self-assembly processes for electronic devices and interconnect. Novel multi-element modules for logic and memory, created by integrating advanced CMOS technology and self-assembly processes, will be designed, fabricated, characterized and optimized for functionality and performance beyond the current lithography limit. Process development will focus on the surface interaction and perturbation that affects the physical mechanism of self-assembly and Ostwald ripening. Two major components to facilitate timely penetration of research to education will be implemented. This is critical for semiconductor research due to the very short life cycle in technology development. First, the open architecture in simulation software will enable graduate and undergraduate students to learn new research models with full numerical functionality and to exchange modules with other for comparison on the same platform.Second, new research trends will help determine core course content and streamline course series to enhance learning efficiency.