CAREER: Interconnect-centric High-Level Synthesis in DSM Regime

由于互连特性在深亚微米状态下占主导地位，我们正在开发一种以互连为中心的高级综合（HLS）框架，其中可以优化延迟，功率和可达性。我们正在研究两种方法：(1)增量方法：HLS通过考虑从详细平面图和全球路线信息中获得的净水平估计来迭代执行；(2)复合方法：将HLS任务（调度、分配和绑定）和物理设计任务（放置和路由）统一到一个复合步骤中。HLS框架的新特点是：(1)在HLS流中使用了详细的互连时序模型（基于矩的、基于Elmore-delay的）；(2)可达性驱动的HLS；(3)使用Rent’s指数作为可达性度量。作为教育计划的一部分，我们正在：(1)开发两个课程序列（双水平）；(2)以案例为基础（哈佛商学院）的教学方式（在MBA领域普遍使用）在VLSI教育中进行试验；(3)让少数民族大学生参与VLSI EDA研究；(4)让K11-12年级的学生接触到VLSI芯片设计自动化领域。

As the interconnect characteristics dominate in deep-sub-micron regime, we are developing an interconnect-centric high-level synthesis (HLS) framework in which delay, power, and routability, can be optimized. We are investigating two approaches: (1) Incremental approach: HLS is performed iteratively by taking into account net-level estimates obtained from a detailed floorplan and global route information; and (2) Composite Approach: HLS tasks (scheduling, allocation, and binding) as well as physical design tasks (placement and routing) are unified into one composite step. The novel features of the HLS framework are: (1) use of detailed interconnect timing models (moment-based, Elmore-delay based) in HLS flow; (2) routability driven HLS; and (3) usage of Rent's exponent as a routability metric. As part of education plan, we are: (1) developing a two course sequence (dual-level); (2) experimenting in VLSI education with the case-based (Harvard Business school) teaching style (popularly used the MBA field); (3) involving undergraduate minority students in VLSI EDA research; and (4) exposing K11-12 students to the field of VLSI chip design automation.