Via-Arrays in Multilayer Substrates for Usage in High-Speed, Energy- and Resource-Efficient Digital Systems

在该后续项目中，将根据新获得的见解改进现有的过孔阵列快速建模算法，并将其应用于能源和资源高效数字系统的分析。通孔阵列是在多层基板（如印刷电路板和多芯片模块）上的多达数千个垂直通孔的规则排列，并且对设计过程提出了严峻的挑战。该项目有以下两个主要目标：第一，通过利用描述过孔阵列行为的矩阵中的现有冗余来进一步加速现有算法。在这里，分层矩阵（所谓的H矩阵）的算术将被应用于实现例程，其中减少了矩阵求逆、矩阵-矩阵乘法和进一步运算的计算工作量。由于通孔阵列建模的固有冗余（例如，由于大量相同的通孔距离），原则上可以预期可以成功地应用分层矩阵。对于H矩阵的构造和上述操作的应用，可以使用莱比锡马克斯普朗克数学科学研究所的HLIB，并将其用作自己编程的基础。第二，针对通孔阵列优化的挑战，对现有算法进行了扩展和调整。这项工作的元素是在多层基板上实现合适的网络端口，通孔阵列的扇出替代品（布线）的自动设计和自动分析链路数据（例如误码率）生成的优化criterial.Both目标有助于直接延续原来的研究计划，并将推进和完成它与近年来获得的新见解。

In this follow-up project an existing algorithm for fast modeling of via-arrays shall be improved on the basis of newly gained insights and shall be applied to the analysis of energy- and resource-efficient digital systems. Via-arrays are regular arrangements of up to several thousand vertical through-holes in multilayer substrates, like printed circuit boards and multi-chip modules, and pose a serious challenge to the design process. The project has the following two main goals: First, the further acceleration of the existing algorithm by making use of the existing redundancies in the matrices that describe the via-array behavior. Here, the arithmetic for hierarchical matrices (so called H-matrices) shall be applied to implement routines with reduced computational effort for matrix inversion, matrix-matrix multiplication and further operations. Due to inherent redundancies of via-array modeling (for example owing to the multitude of identical via distances) it can be expected in principle that hierarchical matrices can be applied successfully. For the construction of H-matrices and for the application of the mentioned operations the HLIB by Max Planck Institute for Mathematics in the Sciences from Leipzig is available and shall be used as a basis for own programming. Second, the extension and adaptation of the existing algorithm in view of the challenges of via-array optimization. Elements of this work are the implementation of suitable network ports in multilayer substrates, the automatic design of fan-out alternatives (wirings) for via-arrays and the automatic analysis of link data (e.g. bit error rates) for generation of optimization criteria.Both goals contribute to a direct continuation of the original research program and will advance and complete it with new insights gained in recent years.