CAREER: INVESTIGATING ELECTROSTATIC DISCHARGE PROTECTION IN ULSI ICs DOWN TO NANO-SCALE: SIMULATION, MODELING & EXPERIMENTS

静电放电（ESD）失效是VDSM（甚深亚微米）和纳米级Si ULSI集成电路技术的一个毁灭性的可靠性问题。研究ESD失效基础和片上ESD保护理论是必要的，重点关注以下挑战：3D混合模式ESD仿真方法；精确的大电流ESD建模；全芯片ESD设计综合，先进的ULSI IC ESD保护解决方案，超ghz RF IC ESD保护，纳米级ESD保护以及宽禁带半导体IC技术。PI提出了解决这些挑战的职业发展计划。提出的研究活动包括六个任务：通过开发一种新的3D混合模式ESD仿真方法，研究ULSI ic中先进的片上ESD保护现象；通过开发精确的大电流ESD器件模型，研究ESD保护原理；开发全芯片ESD设计验证CAD工具ESDcat；探索100nm以下ULSI集成电路的新型超快速ESD保护解决方案，探索未来纳米技术的ESD保护，并将ESD研究扩展到超ghz射频集成电路和宽带隙半导体GaN。由于ESD现象是几何相关的，涉及复杂的电热-工艺-器件-电路耦合，因此提出的研究程序采用全尺寸混合模式方法，以3D格式研究工艺-器件-电路-电子-热全耦合闭环中的ESD基础。为实现大电流ESD的精确建模，提出了一种三维并联ESD模型网络。ESDcat能够在原理图和布局级进行芯片级ESD合成和验证。纳米尺度的静电放电研究将考虑到弹道声子散射效应。用于宽带隙的ESD将重点放在硅兼容GaN集成电路上。最终结果包括对ESD机制的见解，用于进一步研究和设计各种IC技术ESD保护的CAD工具，例如CMOS， BiCMOS， SOI, SiGe, GaN， RFIC和Cu互连。新的ESD理论和直接的工业应用都是值得期待的。教育计划的核心是：新课程开发；微电子研究与教育一体化；学生辅导及社区服务；以及校企合作。具体而言，活动包括：在五年内开发五门课程/实验室；追求改进的微电子教学方法；建立集成电子实验室、虚拟集成电路工厂和TCAD/ECAD设计工作室；指导学生开展跨专业项目；发展本科工业合作项目；让少数族裔/女性学生参与微电子研究。这项为期五年的教育建议已纳入部门的微电子重建计划

Electrostatic Discharge (ESD) failure is a devastating reliability problem to VDSM (very-deep-sub-micron) and nano-scale Si ULSI IC technologies. It is imperative to investigate ESD failure fundamentals and on-chip ESD protection theories focusing on the following challenges: 3D mixed-mode ESD simulation methodology; accurate high-current ESD modeling; whole-chip ESD design synthesis, advanced ESD protection solutions for ULSI ICs, ESDprotection for super-GHz RF ICs, ESD protection for nano-scale as well as wide-bandgap semiconductor IC technologies. The PI proposes a career development plan that addresses these challenges.Proposed research activities consist of six tasks: to investigate advanced on-chip ESD protection phenomena in ULSI ICs by developing a novel 3D mixed-mode ESD simulation methodology; to investigate ESD protection fundamentals by developing accurate high-current ESD device models; to develop a full-chip ESD design verification CAD tool called ESDcat; to explore novel ultra-fast ESD protection solutions for sub-100nm ULSI ICs, to explore ESD protection for future nano-technologies, and to extend ESD research to super-GHz RF ICs and wide-bandgap semiconductor, GaN. Since ESD phenomena are geometry-dependent involving complex electro-thermal-process-device-circuit coupling, the proposed research procedures take full-scale mixed-mode approaches that investigate ESD fundamentals in a fully-coupled process-device-circuit-electronic-thermal closed-loop in 3D format. A 3D parallel ESD model network is proposed for accurate high-current ESD modeling. ESDcat enables chip level ESD synthesis and verification at both schematic and layout levels. Nano-scale ESD research will take into account the ballistic phonon scattering effect. ESD for wide-bandgaps will focus on Si-compatible GaN ICs. End results include insights into ESD mechanisms, CAD tools for further investigation and design of ESD protections for various IC technologies, e.g., CMOS, BiCMOS, SOI, SiGe, GaN, RFIC, and Cu interconnects. Both new ESD theory and immediate industrial applications are expected.The education plan centers on: new curriculum development; integration of microelectronics research and education; student mentoring and community services; and university-industry collaboration. Specifically, activities include: develop five courses/labs in a five-year period; pursue an improved microelectronics teaching approach; establish an Integrated Electronics Laboratory, a Virtual IC Fab facility, and TCAD/ECAD Design Studios; advising students in conducting inter-professional projects; develop a undergraduate industrial co-op program; and involving minority/women students in microelectronics research. This five-year education proposal is integrated into the departmental redevelopment plan in microelectronics