Current Mode Band-Limited Signaling for Deep Submicron Global Interconnects

亚微米CMOS缩放的最新趋势表明，由于增加的信号延迟和串扰噪声，全局互连将日益成为主要的性能限制。铜和低k布线技术的实施减轻了缩放对局部和中间互连中的信号延迟和串扰的影响。然而，由于RC延迟的增加，新材料的益处可能不足以缩放长的全局互连。根据1 TRS路线图，半导体行业为最小化相对延迟而采用的近期解决方案是增加互连的纵横比。然而，金属厚度的增加，随着每一代技术的发展，金属间距的减小和持续的电压缩放将逐渐加剧由于互连电容和电感耦合效应引起的噪声问题，并最终成为局部和全局传播延迟的主要问题。通过引入信号方法的根本变化：使用电流模式带限信号来减少CMOS VLSI中的信号延迟和串扰噪声瓶颈，从而改善了深亚微米互连中的串扰噪声限制。为了减少由于电容和电感效应引起的串扰噪声，基于带限基本波形的所提出的信令方案将部分地取代系统内关键通信链路中的方波脉冲。从建议的带限信号方案在0.35微米CMOS工艺的初步汇款显示铝和铜互连的电容性串扰噪声降低超过30%。一个有吸引力的结果，从所提出的信令方法是，给定的信号带宽和噪声容限的要求，更长的互连线或更高的互连density可以achieved.To克服在深亚微米政权的带宽限制，需要新的方法来高速信令。在本研究中，我们将使用电流模式电路技术来改善频宽效能及减少讯号延迟。电流模式感测在全球互连中的信令受到有限的关注，部分原因是电压模式全摆幅中继器插入方法的流行。.可以看出，随着CMOS技术的不断扩展，实现预期性能标准所需的中继器数量将急剧增加，并构成总系统功耗的重要部分。因此，在深亚微米集成电路时代，电流模式传感电路将越来越受到人们的欢迎。在高性能VLSI系统的早期设计阶段，准确估计长互连线中的传播延迟和串扰噪声起着重要的作用。已经提出了基于模拟和/或解析闭合形式公式的各种技术来对互连中的延迟和串扰进行建模。致力于这一领域的大部分工作都是针对电压模式信号的电容器端接线路。然而，随着VLSI电路中的速度要求的增加，电流模式信号传输技术可以为由激进的互连缩放引起的一些挑战提供有吸引力的解决方案。为了适应电流模式信令技术，我们建议推导出高效的封闭形式的分析模型，驱动分布式RC线与任意终止。这项工作的准确性预测是相同的埃尔默延迟制定，扩展到适应电流模式类型circuits.In这项研究中，我们打算发展的理论基础，建议电流模式带限信令方案和分析制定其影响串扰噪声和信号延迟减少。我们将有针对性地了解其对互连耦合噪声的影响，我们的研究。电路设计问题的研究将遵循原型制造的概念和实验验证。最后，我们打算应用这些知识来建立一个高性能的宽总线系统，以证明降噪的优势。

Recent trends in submicron CMOS scaling suggest that global interconnects will increasingly become a major performance limitation due to increased signal delay and cross-talk noise. The implementation of copper and low k wiring technology mitigates the effect of scaling on signal delay and cross-talk in local and intermediate interconnects. However, the benefits of new materials may not be sufficient for scaling long global interconnects due to the increasing RC delays. The near term solution adopted by the semiconductor industry to minimize the relative delay, according to the 1TRS roadmap, has been to increase the aspect ratio of interconnects. However, the increase in metal thickness, reduction in metal pitch and continuing voltage scaling with each technology generation will progressively exacerbate the noise problem due to interconnect capacitive and inductive coupling effects and will eventually become the dominant problem over local and global propagation delays.The research described in this proposal will address the signal propagation delay and cross-talk noise limitations in deep submicron interconnects by introducing a fundamental change in the signaling approach: the use of current-mode band-limited signaling to reduce the signal delay and cross-talk noise bottlenecks in CMOS VLSI's. To reduce cross-talk noise due to capacitive and inductive effects, the proposed signaling scheme based on band-limited basis waveforms will partially replace the square pulses in critical communication links within the system. A preliminary remit from the proposed band-limited signaling scheme in 0.35-urn CMOS process shows capacitive cross-talk noise reduction beyond 30 percent for aluminum and copper interconnects. An attractive result from the proposed signaling approach is that given the signal bandwidth and noise margin requirements, longer interconnects lines or higher interconnect densities can be achieved.To overcome the bandwidth limitations in the deep submicron regime, new approaches to high-speed signaling are required. In the proposed research, we intend to use current-mode circuit techniques to improve the bandwidth performance and reduce signal delay. Current-mode sensing has received limited attention for signaling in global interconnections partially due to the popularity of voltage-mode full swing repeater insertion methodologies. . It can be shown that as CMOS technology continues to scale, the number of repeaters required to achieve the projected performance criteria will increase dramatically and constitute a significant portion of the total system power dissipation. Therefore, current-mode sensing circuits will increasingly become popular in this deep submicron IC era.Accurate estimation of propagation delay and cross-talk noise in long global interconnects plays an important role in the early design stages of high performance VLSI systems. Various techniques based on simulations and/or analytical closed-form formulations have been proposed to model delay and cross-talk in interconnects. The bulk of the work dedicated to this area targets capacitively terminated lines for voltage mode signaling. However, with the increasing speed requirements in VLSI circuits, current mode signal transporting techniques may provide an attractive solution to some of the challenges caused by aggressive interconnect scaling. To accommodate current-mode signaling techniques, we propose to derive efficient closed-form analytical models for a driven distributed RC line with arbitrary termination. The accuracy of this work is predicted to be the same as Elmore Delay formulation, extended to accommodate current-mode type circuits.In this research, we intend to develop the theoretical basis for the proposed current-mode band-limited signaling scheme and analytically formulate its impact on cross-talk noise and signal delay reduction. We will target our study toward understanding its effects on interconnect coupling noise. Study of circuit design issues will be followed by prototype fabrication for conceptual and experimental verification. Finally, we intend to apply this knowledge to build a high performance wide bus system to prove the noise reduction advantages.