ITR: Optimization of Reconfigurable Architectures for Efficient Implementation of Particle Filters

ABSTRACT0220011DJuric，PetarSUNY@Stony Brook高效实现粒子过滤器的可重构架构的优化近年来，粒子过滤器在几个研究领域引起了极大的关注。这些滤波器用于必须实时处理时变信号的问题，其目的是估计信号的各种未知数并检测由信号描述的事件。在许多应用中，此类问题的标准解是基于卡尔曼或扩展卡尔曼滤波的。在问题高度非线性或使信号失真的噪声是非高斯的情况下，卡尔曼滤波器提供的解决方案可能远远不是最优的。粒子过滤器的一个主要缺点是它们的实现在计算上非常密集。然而，它们本质上是可并行化的，可以为它们的实现构建特殊的硬件，以满足实时处理的严格要求。在这项研究中，开发了可重构且物理上可行的粒子过滤器的VLSI结构。在这些体系结构的发展过程中，对许多重要问题进行了研究。其中最关键的是硬件和软件的平衡，这本身与其他重要问题密切相关。它们包括通过变换和近似降低计算复杂度、研究在滤波器中实现的并行度、研究各种互连机制、随机通信方案、硬件优化以及低功耗VLSI处理器的设计。这项工作还包括构建可重新配置的硬件，使其适用于不同类型的粒子过滤器。

ABSTRACT0220011Djuric, PetarSUNY @ Stony BrookOptimization of Reconfigurable Architectures for Efficient Implementation of Particle FiltersIn recent years particle filters have attracted great attention in several research communities. These filters are used in problems where time-varying signals must be processed in real time and the objective is to estimate various unknowns of the signals and to detect events described by the signals. The standard solutions of such problems in many applications are based on the Kalman or extended Kalman filters. In situations when the problems are highly nonlinear or the noise that distorts the signals is non-Gaussian, the Kalman filters provide solutions that may be far from optimal. A major drawback of the particle filters is that their implementation is computationally very intensive. They are, however, inherently parallelizable, and special hardware can be built for their implementation that can meet the stringent requirements of real-time processing. In this research, reconfigurable and physically feasible VLSI architectures for particle filters are developed. In the development of these architectures, many important problems are researched. The most critical of them is the balancing of hardware and software, which itself is tightly related to other important issues. They include reductions of computational complexities by transformations and approximations, investigation of the degree of parallelism implemented in the filter, investigation of various interconnection mechanisms, random communication schemes, hardware optimization, and design of low power VLSI processors. This effort also includes building of reconfigurable hardware so that it is suitable for different types of particle filters.