Performance Analysis and Optimization for Nanometer Design

摘要在不远的将来，半导体设计有望在一块芯片上集成数十亿个晶体管，并将以超过10 GHz的频率工作。这一巨大的进步将带来不可预见的挑战，并将要求用于设计高性能处理器的工具和方法发生巨大变化。由于工作频率较高，因此必须对设计进行准确的性能验证。同时，由于同一芯片上紧密间隔的器件之间的耦合，设计中的噪声将上升到惊人的新水平。高噪声电平将通过减慢电路中的关键延迟路径来影响性能，因此将威胁到可实现的工作频率。因此，我们提出了在高噪声水平下分析处理器性能的新方法。此外，我们打算为未来的高性能处理器和片上系统设计开发新的噪声控制电路环境中的性能优化方法。

AbstractIn the not too distant future, semiconductor designs are expected to integrate billions of transistors on a single chip and will operate at frequencies in excess of 10GHz. This dramatic progress will introduce unforeseen challenges and will require dramatic changes of the tools and methods used to design highperformance processors. With high operating frequencies, accurate performance verification of the design will be come paramount. At the same time, noise in the design will rise to dramatic new levels due to the coupling between closely spaced devices on the same die. High noise levels will impact the performance by slowing down the critical delay paths in a circuit and will therefore threaten the achievable operating frequencies. We therefore propose new methods for the analysis of processor performance in the presence of high-noise levels. Furthermore, we intend to develop new methods for performance optimization in noise dominated circuit environments for future high-performance processor and systems-on-chip designs.