Hybrid External/Built-In Self-Test Techniques

随着测试新一代复杂片上系统（SOC）设计所需的测试数据量持续快速增长，传统的外部测试方法（所有测试数据存储在测试仪上并传输到/从芯片）变得越来越困难。测试器的速度、内存和I/O通道有限。测试器和芯片之间有限的测试数据带宽正在成为一个主要的瓶颈，预计会变得更糟。该项目涉及开发混合方案，以新颖的方式将外部测试和自我测试方法结合起来，以减轻外部测试人员的负担。这种技术可以提供两全其美的效果。通过智能地利用来自测试人员的确定性数据来指导自检硬件，可以克服自检方法的开销和故障覆盖限制，同时可以将外部测试人员的测试数据带宽和存储需求降低几个数量级。在本研究中需要回答的一些问题包括：1。使用来自测试器的确定性数据来指导芯片上的测试模式生成硬件的最有效方法是什么？如何在测试数据带宽受限的情况下最小化硬件。对于具有多个核心的片上系统（SOC），为每个核心配置混合测试硬件的最佳方法是什么？如何使用来自测试仪的确定性数据来减少自测期间的功耗？如何用混合方案提高延迟故障覆盖率。

As the amount of test data required to test new generations of complex system-on-chip (SOC) designs continues to grow rapidly, conventional external testing approaches where all test data is stored on the tester and transferred to/from the chip is becoming increasingly difficult. Testers have limited speed, memory, and I/O channels. The limited test data bandwidth between the tester and the chip is becoming a major bottleneck that is projected to become much worse. This project involves developing hybrid schemes that combine external testing and self-testing approaches in novel ways to ease the burden on the external tester. Such techniques can provide the best of both worlds. The overhead and fault coverage limitations of self-test approaches can be overcome by intelligently making use of deterministic data from the tester to guide the self-test hardware, while the test data bandwidth and storage requirements for the external tester can be reduced by orders of magnitude. Some of the questions to be answered in this research include: 1. What are the most efficient ways to use deterministic data from the tester to guide test pattern generation hardware on the chip.2. How to minimize the hardware under a constraint on test data bandwidthfrom the tester.3. For a system-on-chip (SOC) with multiple cores, what is the best way toconfigure the hybrid test hardware for each core.4. How can deterministic data from the tester be used to reduce powerdissipation during self-test.5. How can delay fault coverage be improved with a hybrid scheme.