SHF:Small: Reducing Test Time and Improving Diagnosis for Increasingly Dense ICs

随着技术规模的扩大，测试和诊断集成电路所需的数据量继续急剧增长，这不仅是因为更大的设计，而且还因为需要额外的测试来针对新的缺陷。集成电路密度的增长速度继续快于自动测试设备(ATE)和待测芯片之间的测试数据带宽，这受到测试仪上的通道数和芯片上的管脚数量的限制。该项目涉及开发新的数据压缩和提取方法，这些方法从根本上不同于现有技术，能够更有效地减少数据量，显着改善测试时间和诊断准确性。该项目将为研究生和本科生提供关于最新设计和测试技术的高级培训，包括那些来自代表性不足群体的学生。该项目将研究几个新的研究方向，以改进测试数据的压缩和提取。将研究一种使用符号抵消从线性签名中提取信息的全新方法，以找到错误位置以帮助诊断。通过将来自签名的信息与来自电路的结构信息相结合，可以实现更高的诊断精度。将通过新的概念改进测试压缩，包括(I)测试激励解压缩和输出响应压缩之间的带宽共享，(Ii)线性和非线性编码的组合，(Iii)低扇出响应压缩体系结构，以及(Iv)从线性压缩器的动态提取。本项目中开发的新技术和体系结构将被实施，并对其性能进行评估。

The amount of data required to test and diagnose integrated circuits continues to grow dramatically as technology scales, not only because of larger designs, but also the need for additional tests to target new defects. The density of ICs continues to grow faster than the test data bandwidth between automatic test equipment (ATE) and the chip-under-test, which is constrained by the number of channels on the tester and pins on the chip. This project involves developing new approaches for compression and extraction of data that are fundamentally different from existing techniques and capable of more efficiently reducing the amount of data and significantly improving test time and diagnosis accuracy. The project will provide advanced training to both graduate and undergraduate students, including those from underrepresented groups, in the latest design and test technologies.Several new research directions for improving compression and extraction of test data will be investigated in this project. A fundamentally new approach for extracting information from linear signatures using symbolic canceling will be studied for finding error locations to aid in diagnosis. By combining information from the signature together with structural information from the circuit, much greater diagnostic precision is possible. Improvements in test compression will be pursued through new concepts including (i) bandwidth sharing between test stimulus decompression and output response compaction, (ii) combining linear and non-linear encoding, (iii) low fan-out response compaction architectures, and (iv) dynamic extraction from linear compactors. The new techniques and architectures developed in this project will be implemented and their performance evaluated.