CAREER: Design-For-Testability in Core-Based Designs

为了缩短集成电路和系统的产品开发周期，预先设计的核被广泛用作片上逻辑的一部分。测试基于核心的设计是一个主要问题，因为核心的内部设计可能不知道是否是知识产权。在这种情况下，标准的生产测试策略将是不够的。这项研究正在探索新的方法来测试芯片与嵌入式核心。该方法是找到合成的用户定义的逻辑，在核心驻留的方法，使整个设计满足面积，性能和测试标准。正在开发的合成算法解决了 以下关注：1.将测试向量应用于核心的输入。 2.观察驱动内核输入的用户定义逻辑的输出。 3.测试由核心输出驱动的用户定义逻辑。 4.观察核心产出。

In order to shorten product development cycles for integrated circuits and systems, pre-designed cores are widely used as part of the on-chip logic. Testing core-based designs is a major issue because the internal design of the core may not be known if it is intellectual property. In that case standard manufacturing test strategies will not suffice. This research is exploring new methodologies for testing chips with embedded cores. The approach is to find methods for synthesizing the user-defined logic, in which cores reside, so that the whole design meets area, performance and test criteria. Synthesis algorithms are being developed which address the following concerns: 1. Application of test vectors to inputs of the core. 2. Observation of outputs from the user-defined logic that drive the inputs of the core. 3. Testing the user-defined logic driven by the outputs of the core. 4. Observation of outputs from the core.