ITR - (ASE) - (int): CAD for Reducing Soft Error Failure Rates in Logic Circuits

ITR - (ASE) - (int)：用于降低逻辑电路中软错误故障率的 CAD

• 批准号: 0426608
• 负责人: Nur Touba
• 金额: $ 35万
• 依托单位: University of Texas at Austin
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2004
• 资助国家: 美国
• 起止时间: 2004-09-01 至 2009-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0426608&HistoricalAwards=false
• 关键词: ITR; ASE; int; CAD; Reducing

Proposal ID: 0426608 P I: Touba, Nur Organization: University of Texas at Austin Title: ITR - (ASE) - (int): CAD for Reducing Soft Error Failure Rates in Logic Circuits Abstract:Reducing the soft error failure rate for logic circuits is more expensive and difficult than for memories and is expected to emerge as a very important problem in the future for mainstream low-cost electronics as technology continues to scale. Currently, there is a lack of computer-aided design (CAD) tools and techniques for addressing this problem in a cost-effective manner. This research project involves developing a new paradigm for designing logic circuits with protection from soft errors to reduce the soft error failure rate. A fine-grain quantitative approach will be investigated where the susceptibility of the logic circuit to soft errors is estimated at each step of the design process and fault tolerance features are incorporated as needed in a cost effective way to satisfy soft error failure rate requirements. One of the key ideas in this research is to exploit the asymmetric soft error susceptibility of internal nodes in a logic circuit to direct the insertion of fault tolerance features. Unlike memories where the probability of a soft error in each cell is equally likely, in logic circuits upsets at some internal nodes can have orders of magnitude greater probability of being latched and causing a soft error than at other nodes. By focusing error detection and/or error masking capability towards the nodes that are most susceptible to soft errors, the soft error failure rate in logic circuits can be significantly reduced at a fraction of the cost of existing techniques which try to guarantee coverage of all nodes. The objectives of this project include developing efficient procedures for estimating soft error susceptibility, developing CAD algorithms for cost-effective insertion of fault tolerance features, and developing soft error protection schemes that minimize impact on timing and power.

提案ID：0426608 P I：Touba，Nur组织：德克萨斯大学奥斯汀分校标题：ITR-(ASE)-(INT)：用于降低逻辑电路中的软错误故障率的计算机辅助设计摘要：降低逻辑电路的软错误故障率比降低存储器的软错误故障率更昂贵和更困难，随着技术的不断扩大，预计未来将成为主流低成本电子产品的一个非常重要的问题。目前，缺乏以具有成本效益的方式解决这一问题的计算机辅助设计(CAD)工具和技术。这项研究项目涉及开发一种新的设计范例，用于设计具有软错误保护的逻辑电路，以降低软错误故障率。将研究一种细粒度定量方法，其中在设计过程的每个步骤估计逻辑电路对软错误的敏感度，并根据需要以经济高效的方式结合容错特征以满足软错误故障率要求。本研究的核心思想之一是利用逻辑电路内部节点的非对称软错误敏感性来指导容错特征的插入。与在每个单元中软错误的概率相同的存储器不同，在逻辑电路中，在一些内部节点处的扰乱可能具有比在其他节点处更大的锁存和引起软错误的概率数量级。通过将错误检测和/或错误掩蔽能力集中到最容易受到软错误影响的节点，可以以试图保证覆盖所有节点的现有技术的一小部分成本显著降低逻辑电路中的软错误故障率。该项目的目标包括开发用于估计软错误敏感性的有效程序，开发用于经济高效地插入容错功能的CAD算法，以及开发将对定时和功率的影响降至最低的软错误保护方案。