Bringing Low Power Reconfigurable Analog Signal Processing to Embedded Systems

可重构模拟技术的现代进步使得现场可编程模拟阵列（FPAA）能够显著降低功耗，同时增加尺寸、灵活性和实用性。 本项目的目标是开发第一个基于浮栅的大规模FPAA的映射算法。 目标FPAA器件由浮栅晶体管组成，浮栅晶体管是标准pFET器件，其栅极端子不连接到信号，除非通过电容器。 由于栅极端子与外部信号绝缘良好，因此浮置栅极可以保持永久电荷。 FPAA中的计算逻辑被组织在一个紧凑的计算模拟模块（CAB）中，该模块由运算放大器、晶体管、乘法器、可编程电容和滤波器组成。 CAB以规则的网状结构平铺在芯片上，其间有总线和局部互连。 FPAA芯片上的主要寄生效应是由于FPAA互连线上的寄生电阻和寄生电容。 因此，映射过程中的主要目标是尽量减少每个互连中涉及的无线和交换机的总数。 映射过程分为三个部分：CAP聚类、CAP放置和FPAA路由。 CAB聚类算法尝试在器件和导线约束下将给定电路中的模拟元件分组到CAB聚类中。 在CAP放置过程中，每个CAB集群被分配到给定FPAA架构中的唯一CAB插槽，以便同时最大限度地减少线长、拥塞和性能下降。 FPAA路由器最初通过最短路径路由每个互连，同时忽略路由资源的任何过度使用。 然后，它依次执行每个连接的拆分和重新路由，以最大限度地减少路由解决方案中路由资源的过度使用。 拟议的测绘技术正在转让给一家初创公司，工具和培训材料通过在线流媒体视频课程广泛提供。 参与的研究生将获得数字/模拟信号处理、混合信号系统设计和物理布局自动化算法方面的经验。

Modern advances in reconfigurable analog technologies are allowing field-programmable analog arrays (FPAAs) to dramatically reduce the power consumption while growing in size, flexibility and usefulness. The goal of this project is to develop the first mapping algorithm for floating-gate-based large-scale FPAAs. The target FPAA device consists of floating-gate transistors, which are standard pFET devices whose gate terminals are not connected to signals except through capacitors. Because the gate terminal is well insulated from external signals, the floating gate can maintain a permanent charge. The computational logic in the FPAA is organized in a compact computational analog block (CAB) that consists of op-amps, transistors, multiplier, programmable capacitors, and filters. CABs are tiled across the chip in a regular mesh-type architecture with busses and local interconnects between them. The major parasitic effects on FPAA chips are due to parasitic resistance and capacitance on FPAA interconnects. Therefore, the primary objective during mapping is to minimize the total number of wireless and switches involved in each interconnect. The mapping process is divided into three: CAP clustering, CAP placement, and FPAA routing. The CAB clustering algorithm tries to group analog components in the given circuit into CAB clusters under the device and wire constraints. During CAP placement, each CAB cluster is assigned to a unique CAB slot in the given FPAA architecture so that the wirelength, congestion, and performance degradation are minimized simultaneously. The FPAA router initially routes each interconnect by the shortest path while ignoring any overuse of routing resources. Then it sequentially performs ripping-up and re-routing every connection to minimize overuse of routing resources in the routing solution. The proposed mapping technology is being transferred to a startup company, and tools and training materials are made widely available through an on-line streaming video course. Graduate students involved are gaining experience in digital/analog signal processing, mixed-signal system design, and physical layout automation algorithms.