CAREER: A Framework for Early-Stage Computer Architecture Design Space Exploration and Optimization

摘要高性能、消费类和嵌入式计算的未来发展将受到功率和热问题的限制。当我们寻求为这些领域开发新的计算设备时，在设计和开发过程的早期阶段了解功率需求是至关重要的。该项目将开发一个准确而灵活的建模基础设施，可用于量化功率、性能和设计复杂性，并将利用该基础设施探索未来的功率感知计算设计决策。该项目旨在开发新的技术解决方案，以解决建筑功率和周期时间建模以及量化设计复杂性的问题。所提出的模型结合了分析模型的灵活性优势和完全经验模型提供的优越精度。在这种方法中，在构建模块上对有功功率、泄漏功率和延迟进行详细的经验表征，然后开发分析模型，将它们适当地链接到微建筑结构模型中。这些模型将应用于研究架构设计在功率、性能和设计复杂性之间的权衡。特别是，该项目旨在了解嵌入式和高性能架构的相对功率性能效率和设计复杂性，以及在指令和线程级别提取并行性的方法。

CAREER: A Framework for Early-Stage Computer Architecture Design Space Exploration and Optimization AbstractFuture advances in high-performance, consumer, and embedded computing will be limited by power and thermal issues. As we seek to develop novel computing devices for these domains, it is critical to understand the power requirements at the earliest stages of the design and development process. This project will develop an accurate and flexible modeling infrastructure that can be used to quantify power, performance, and design complexity and will utilize this infrastructure to explore future power-aware computing design decisions.This project seeks to develop novel technical solutions to architectural power and cycle-time modeling and to the problem of quantifying design complexity. The proposed models combine the flexibility advantages of analytical models with the superior accuracy that fully-empirical models provide. In this methodology, detailed empirical characterization of active power, leakage power, and delay is performed on building blocks and analytical models are then developed to chain them appropriately to model microarchitectural structures. These models will be applied to study architectural design tradeoffs between power, performance, and design complexity. In particular, this project seeks to understand the relative power-performance efficiency and design complexity of embedded and high-performance architectures and methods for extracting parallelism at the instruction and thread-level.