International Symposium on High Dielectric Constant Gate Stacks will be held in Los Angeles, California on October 16-21, 2005.

ECS-0535679本提案要求提供资金，以支持作为电化学学会第208次会议一部分举行的第三届高介电常数栅极堆国际研讨会。2005年10月16日至21日，加州，洛杉矶。更具体地说，所要求的资金（$3，955.00）将用于资助最多5名优秀研究生/本科生的部分差旅费，以及25名已确认的受邀演讲者中仅3名受邀演讲者的注册豁免。本次研讨会将讨论先进栅堆栈的基础科学和最新技术，用于互补金属氧化物半导体（CMOS）和亚微米存储器应用。65 nm特征尺寸集成电路，包括：（1）衬底：高迁移率半导体，如应变Si、Si（110）和（111）、SiGe、Ge和III-V族化合物、GeOI、绝缘体上GaAs和SOI。(2)高k栅介质材料和工艺：65 nm及以上高k栅介质技术的趋势，新型高k材料，65 nm及以上先进的氮氧化物，高k栅介质生长技术，高k栅介质沉积方法，先进的CVD前体。(3)栅电极材料和工艺：65纳米及以上的栅电极技术趋势;多晶硅、硅化和金属栅电极，带边和带隙中功函数材料，栅电极沉积方法。(4)高K栅介质界面：硅/高K和高K/栅电极界面氧扩散和界面层形成机制界面制备，钝化，工程和控制。(5)先进的栅极堆栈可靠性：低电压应用中主要可靠性问题的识别和新的可靠性模型偏压温度不稳定性金属交叉污染跨层电子迁移率退化机制新材料的热稳定性. (6)高K栅电介质特性和方法：先进的物理，化学和电特性的栅堆栈准确确定介电电容陷阱参数提取非接触式电特性功函数提取方法的确定Tunnel电子/空穴质量。(7)动态随机存取记忆体与非挥发性记忆体材料：高K动态随机存取记忆体电容器技术的趋势，电极/介电化学交互作用，结构的热稳定性，非挥发性与新型记忆体应用。

ECS-0535679This proposal requests funds to support the International Symposium on HIGHDIELECTRIC CONSTANT GATE STACKS III to be held as part of 208th Meeting ofThe Electrochemical Society, Inc. Los Angeles, California, October 16-21, 2005. Morespecifically, the funds requested ($3,955.00) will be utilized for partial support of thetravel expenses for up to five deserving graduate/undergraduate students and registrationwaiver for only 3 invited speakers out of 25 confirmed invited speakers.This symposium will address the fundamental science and recent technologies ofadvanced gate stacks for complementary metal-oxide-semiconductor (CMOS) andmemory applications in sub-65 nm feature size integrated circuits, including: (1)Substrates: Higher mobility semiconductors such as strained Si, Si(110) and (111), SiGe,Ge and III-V compounds, GeOI, GaAs-on-insulator, and SOI. (2) High k Gate DielectricMaterials and Processing: Trends in high k gate dielectric technologies for 65 nm andbeyond, novel high k materials, advanced oxynitrides for 65 nm and beyond, high k gatedielectric growth techniques, high k gate dielectric deposition methods, advancedprecursors for CVD. (3) Gate Electrode Materials and Processing: Trends in gateelectrode technologies for 65 nm and beyond; poly-Si, silicided, and metal gateelectrodes, band-edge and midgap work-function materials, gate electrode depositionmethods. (4) High K Gate Dielectric Interfaces: Silicon/High-K and High-K/Gate-Electrode Interfaces Oxygen Diffusion and Mechanisms of Interface Layer FormationInterface Preparation, Passivation, Engineering, and Control. (5) Advanced Gate StackReliability: Identification of Main Reliability Problems in Low Voltage Application andNew Reliability Models Bias Temperature Instability Metallic Cross-ContaminationAcross Layers Mechanisms of Electron Mobility Degradation Thermal Stability of NewMaterials. (6) High K Gate Dielectric Characterization and Methodologies: AdvancedPhysical, Chemical, and Electrical Characterization of Gate Stacks AccurateDetermination of Dielectric Capacitance Trap Parameter Extraction Non-ContactElectrical Characterization Work-function Extraction Methodologies Determination ofTunneling Electron/Hole Mass. (7) DRAM and Non-Volatile Memory Materials: Trendsin High K DRAM Capacitor Technologies Electrode/Dielectric Chemical InteractionsThermal Stability of Structures Non-Volatile and Novel Memory Applications.