CSR-AES: Parallelizing Irregular Applications for Multicore Processors

NSF Award Abstract计算机工业正在发生根本性的变化。CPU芯片制造商没有提高时钟频率，而是利用半导体技术的进步来增加处理器芯片上的内核数量。这将提高程序性能的负担从芯片制造商转移到了软件开发商身上。许多业内专家认为，对多核处理器进行编程是软件行业目前面临的最重要挑战。并行架构的并行技术对于使用树和图等链接数据结构的不规则应用程序无效。这些数据结构普遍存在于图形学、网格生成和线性系统求解器等重要应用领域。本项目开发了一种新的方法，用于多核处理器上的并行化和优化不规则程序。关键的见解是乐观并行化对于不规则程序是必不可少的。事务性内存是实现乐观并行化的一种有吸引力的方式;本项目将设计、实现和评估新的事务性模型，这些模型利用高级程序抽象的属性，而不是简单地跟踪低级读写。结果将通过发布和提供软件事务性内存系统供下载来传播。向主要公司转让技术是传播成果的另一个途径。

NSF Award AbstractThere is a fundamental change ongoing in the computer industry. Instead of increasing clock frequency, which increases power dissipation, CPU chip manufacturers are using advances in semiconductor technology to increase the number of cores on a processor chip. This shifts the burden of improving program performance from chip manufacturers to software developers. Many industry experts believe that programming multicore processors is now the most important challenge facing the software industry.Compiler technology for parallel architectures is not effective for irregular applications that use linked data structures such as trees and graphs. These data structures are ubiquitous in important application areas like graphics, mesh generation and linear system solvers.This project develops a new approach for parallelizing and optimizing irregular programs for multicore processors. The key insight is that optimistic parallelization is essential for irregular programs. Transactional memory is an attractive way to implement optimistic parallelization; this project will design, implement and evaluate new transactional models that exploit properties of high-level program abstractions rather than simply tracking low-level reads and writes.Results will be disseminated through publications and by making the software transactional memory system available for downloading. Technology transfer to leading companies is another avenue for disseminating results.