CAREER: Process Variation Aware Embedded MPSoC Synthesis

这项NSF CAREER研究的目标是为纳米级CMOS技术的嵌入式系统综合开发工艺变化感知设计方法。许多嵌入式系统是异构的多处理器片上系统（MPSoC）架构。嵌入式多处理器片上系统的制造依赖于深亚微米工艺技术，这引起了对工艺变化的担忧，这可能导致设计的显着性能变化。尽管针对最坏情况的工艺边界进行设计是处理异常值的传统方法，但在新工艺技术中遇到的可变性程度使这种选择不可行。现有的确定性嵌入式系统设计方法，由于过于保守的设计方法，可能会导致意想不到的性能差异或悲观的性能估计，并可能最终使用过多的资源来保证实时约束。这项研究提出了一种设计范式的转变，从今天的确定性设计到统计或概率设计。具体而言，本提案旨在：(1)开发分层统计分析方法，以促进嵌入式MPSoC的合成；(2)开发过程变化感知硬件综合技术；(3)针对嵌入式应用开发过程变化感知软件最坏情况执行时间（WCET）分析与优化技术；(4)开发过程变化感知软硬件协同合成技术。该计划的教育部分包括：通过整合流程变化的新课程模块来增强现有课程，以补充和升级核心课程；通过研究出版物、课程、研讨会、教程和讲习班广泛传播研究成果；以及软件组件的开发，这些组件被传播到研究社区和其他地方。

The objective of this NSF CAREER research is to develop process variation aware design methodologies for the synthesis of embedded systems in nanometer scale CMOS technology. Many embedded systems are heterogeneous multiprocessor system-on-chip (MPSoC) architectures. The reliance on deep sub-micron process technologies for the fabrication of embedded multiprocessor system-on-chips gives rise to concerns about process variations, which can cause significant performance variations for a design. Although designing for worst-case process margins is the traditional approach to deal with outliers, the degree of variability encountered in the new process technologies makes this option nonviable. The existing deterministic embedded system design methodologies may result in unexpected performance discrepancy or a pessimistic performance estimation, and may end up using excess resources to guarantee real-time constraints, due to overly conservative design approaches. This research proposes a design paradigm shift from today's deterministic design to statistical or probabilistic design. Specifically, this proposal aims at: (1) developing hierarchical statistical analysis methodologies to facilitate embedded MPSoC synthesis; (2) developing process-variation-aware hardware synthesis techniques; (3) developing process variation aware software worst case execution time (WCET) analysis and optimization techniques for embedded applications; (4) developing process variation aware hardware/software co-synthesis techniques. The education part of this program includes: the enhancement of existing curriculum by integrating new course modules on process variations to complement and upgrade the core courses; the broad dissemination of the results via research publications, courses, seminars, tutorials, and workshops; and the development of software components that are disseminated to the research community and beyond.