CPA: Collaborative Research: Formal Techniques for Designing Globally Asynchronous and Locally Synchronous Systems (FMGALS)

协作提案ID： 0702316和0702539题目：：合作研究：设计全局异步和局部同步系统（FMGALS）PI的形式化技术：Sandeep K. Shukla（弗吉尼亚理工大学）Kenneth Stevens（犹他州大学）全球异步和本地同步（GALS）设计的增长势头是由三个因素推动的。首先，由于CMOS技术的特征尺寸的减小以及千兆赫范围内的时钟频率的增加，时钟周期朝向在整个芯片中的有效同步时钟变得困难的极限减小。其次，如果所有IP不必针对相同的时钟方案进行优化，则基于IP重用的SoC设计变得更容易，最后，时钟缓冲器、全局中继器和时钟树中的功耗增加是日益增长的工业关注。然而，正确设计GALS系统容易出错并且困难。除了少数例外，学术界之外几乎不存在异步设计工具和方法。研究GALS设计的工具和方法势在必行。考虑到这些问题的微妙性和复杂性，我们认为将任何GALS方法学建立在正式方法中是重要和必要的。 真实的实现协议到片上结构和实验验证的有效性，这种设计是必要的广泛接受的设计方法。在这个项目中，弗吉尼亚理工大学和州立大学和犹他州大学的团队将合作开发一个正式的基础，设计和实验的权衡各种GALS解决方案，并且实际上在芯片上制造这样的解决方案以校准解决方案。除了发明新的GALS技术的研究和教育影响，以及用于正式捕获协议并验证它们的方法，这个项目的更广泛的影响将包括协作团队工作和训练学生在分布式开发环境中工作，将本科研究人员纳入研究，并特别努力将少数民族学生纳入该项目。

Collaborative Proposal ID(s): 0702316 and 0702539Title:: Collaborative Research: Formal Techniques for Designing Globally Asynchronous and Locally Synchronous Systems (FMGALS)PIs: Sandeep K. Shukla (Virginia Tech) & Kenneth Stevens (University of Utah)The increased momentum towards Globally Asynchronous and Locally Synchronous(GALS) design has been necessitated by three factors. First, due to decreasing feature size of CMOS technology, and increasing clock frequency in the gigahertz range, the clock period is diminishing towards a limit where efficient synchronous clocking throughout the chip is getting difficult. Second, IP reuse based System on Chip (SoC) design becomes easier if all IPs do not have to be optimized for the same clocking scheme, and finally, increasing power consumption in clock buffers, global repeaters and clock tree is a growing industrial concern.However, correctly designing GALS systems is error prone and difficult.Asynchronous design tools and methodologies are almost nonexistent outside academia with a few exceptions. Research towards tools and methodologies for GALS design is imperative. Given the subtlety and complexity of these problems, we believe that grounding any GALS methodology in formal methods is important and necessary. Real implementation of protocols into on-chip fabrics and experimental validation of the efficacy of such designs is necessary for the wide acceptance of the design methodologies.In this project, the Virginia Polytechnic and State University and the University of Utah teams will collaborate to develop a formal basis for designing and experimenting with the trade-offs of various GALS solutions, and actually fabricate such solutions on-chip to calibrate the solutions.Other than the research and educational impact of inventing new GALS techniques, and methodologies for formally capturing the protocols and verifying them, the broader impact of this project will constitute collaborative team work and training of students to work in a distributed development environment, inclusion of undergraduate researchers into research, and special effort of including minority students into the project.