Architectural Support for Parallelism on Multi-Core Architectures

工业正在从面向单处理器的处理器转向在单个芯片上执行多个线程的架构。这包括多线程处理器和越来越多的多核处理器。也就是说，晶体管数量和密度的增加不再适用于单cpu或单线程性能的提高。相反，这些晶体管被用于增加可用执行上下文的数量。这种技术转变最重要的影响是，微处理器只有在具有丰富的线程级并行性的情况下才能继续提高性能。对于许多工作负载，可用的并行性很快就会低于硬件能够利用的并行性。在这些环境中，未来几代处理器的性能进步将变得不可用。这种并行差距是不可避免的，因为我们在芯片上可以放置多少上下文并没有明确的限制。这项研究将创建一个解决方案工具箱，使有效地利用片上并行性来提高性能、功率效率和程序的正确性。特别强调的是传统的并行方法已经无效的应用。本研究将重点研究以下几个方面的解决方案。更高效的并行架构通过确保并行运行的程序尽可能有效地利用可用的并行性，从而更好地利用可用的并行性。非传统的并行形式允许多个上下文提供加速，而不必脱离单一执行流模型。动态生成的并行性将使用轻量级硬件监视器来识别可能与内存无关的代码，单独的线程将分析并可能重写代码以动态地利用并行性。除了提供性能之外，还可以利用多核架构来提供在单核上不可能实现或不具有性能效益的新功能。该功能包括软件容错、调试和安全性。

Industry is shifting from uniprocessor-oriented processors to architectures which execute multiple threads on a single chip. This includes multithreaded and, increasingly, multiple-core processors. That is, increases in transistor count and density are no longer being applied to increased single-cpu or single-thread performance. Instead, those transistors are being used to increase the number of available execution contexts. The most significant impact of this technology shift is that microprocessors will only continue to scale in performance in the presence of abundant thread level parallelism.For many workloads, the parallelism available will quickly fall short of the parallelism the hardware is able to exploit. The performance advances of future processor generations then become unavailable in those environments. This parallelism gap is inevitable, because there is no clear limit in sight to how many contexts we can place on a chip.This research will create a toolchest of solutions to enable the effective use of on-chip parallelism to improve performance, power efficiency, and correctness of programs. Particular emphasis is on applications for which traditional methods of parallelism have been ineffective. This research will focus on solutions in the following areas. More efficient parallel architectures enable better exploitation of available parallelism by ensuring that what does run in parallel does so as effectively as possible. Non-traditional forms of parallelism allow multiple contexts to provide speedup, without necessarily departing from the single execution stream model. Dynamically-generated parallelism will use lightweight hardware monitors to identify code that is potentially memory-independent, and separate threads will analyze and possibly rewrite the code to exploit the parallelism dynamically. In addition to providing performance, multi-core architectures can be exploited to provide new functionality that either is not possible, or not performance-effective, on a single core. This functionality includes software fault tolerance, debugging, and security.