Hardware Generation of Threads in a Multithreading Processor

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Simultaneous Multithreaded (SMT) processors depend on thread- level parallelism (multiple jobs to run) to surpass the performance of single-threaded processors. However, single- thread performance is still important for mainstream processors. When there are only one or a few processes in the system, hardware can create threads that increase the ILP available to the SMT processor, using otherwise idle resources. This project is developing hardware thread- generation techniques to increase SMT performance in the absence of software-generated thread-level parallelism. The techniques being investigating include multiple path execution, instruction recycling, and speculative loop execution. Threaded Multiple-path Execution (TME) takes advantage of idle hardware contexts to solve the branch problem, speculatively executing multiple paths through conditional branches in a single application. Instruction Recycling increases the efficiency of multiple-path execution, as it avoids refetching instructions which are not path-dependent on a branch, and avoids re-executing instructions that are not data-dependent on the branch. Speculative Loop Parallelism speculatively executes multiple future loop iterations in parallel, using compiler analysis and dynamic hardware detection of loops and induction statements.