Context-Sensitive Decoding: Exploiting Translated ISAs for Security, Safety, Energy, and Performance

上下文相关解码：利用翻译后的 ISA 来实现安全、安全、能源和性能

• 批准号: 1652925
• 负责人: Dean Tullsen
• 金额: $ 30万
• 依托单位: University of California-San Diego
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2016
• 资助国家: 美国
• 起止时间: 2016-10-01 至 2019-09-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1652925&HistoricalAwards=false
• 关键词: Context; Sensitive; Decoding; Exploiting; Translated

Context-Sensitive Decoding allows a processor with a translated instruction set architecture (such as x86, and often ARM) to decode a given instruction into a different set of micro-ops, depending on conditions set, for example, by the operating system. This allows the system to transparently add features (for security, performance, energy efficiency, debugging, etc.) to executing code with no changes to the code or access to the original sources. It could be used to add security features to unknown code with significantly reduced cost, and thus move closer to the point where such security can be always turned on. Context-sensitive decoding can be used to add a level of specialization to general-purpose processors (an industry dominated by US-based companies) that better enables them to compete with domain-specific specialized solutions, with no significant changes to current pipelines.Many modern processors translate the programmer-visible instruction set architecture (ISA) to a separate, simpler internal ISA. This research makes that traditionally static translation dynamic, where instructions can be decoded/translated differently based on context. For example, we can seamlessly transition from a performant (traditional) translation to a secure translation that now includes data address randomization by setting a single flag in the processor. In addition to security, other applications abound in areas such as programming languages (e.g., on demand type safety, range checking, etc.), software engineering (full-performance debug mode), profiling and performance programming (performance counters of much greater variety than supported natively in hardware, seamlessly enabled or disabled), etc.

上下文敏感解码允许具有转换指令集架构（例如x86，通常是ARM）的处理器根据例如操作系统设置的条件将给定指令解码为不同的微操作集。 这允许系统透明地添加功能（用于安全性、性能、能效、调试等）。在不改变代码或访问原始源代码的情况下执行代码。 它可以用于以显著降低的成本向未知代码添加安全特性，从而更接近于始终可以打开这种安全性的点。（这是一个由美国公司主导的行业），使他们能够更好地与特定领域的专业解决方案竞争，许多现代处理器将程序员可见的指令集架构（伊萨）转换为单独的、更简单的内部伊萨。这项研究使传统的静态翻译成为动态的，其中指令可以根据上下文进行不同的解码/翻译。 例如，我们可以通过在处理器中设置单个标志，从高性能（传统）转换无缝地转换到现在包括数据地址随机化的安全转换。 除了安全性之外，其他应用在诸如编程语言（例如，按需类型安全、范围检查等），软件工程（全性能调试模式）、剖析和性能编程（性能计数器的种类比硬件中本机支持的要多得多，可以无缝地启用或禁用）等。

项目成果

Virtual Melting Temperature: Managing Server Load to Minimize Cooling Overhead with Phase Change Materials

• DOI: 10.1109/isca.2018.00013
• 发表时间: 2018-06
• 期刊: 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA)
• 作者: Matt Skach;Manish Arora;D. Tullsen;Lingjia Tang;Jason Mars

Prime+Abort: A Timer-Free High-Precision L3 Cache Attack using Intel TSX

• 发表时间: 2017-08
• 作者: Craig Disselkoen;David Kohlbrenner;Leo Porter;D. Tullsen

Composite-ISA Cores: Enabling Multi-ISA Heterogeneity Using a Single ISA

• DOI: 10.1109/hpca.2019.00026
• 发表时间: 2019-02
• 期刊: 2019 IEEE International Symposium on High Performance Computer Architecture (HPCA)
• 作者: A. Venkat;H. Basavaraj;D. Tullsen

Deciphering Predictive Schedulers for Heterogeneous-ISA Multicore Architectures

解读异构 ISA 多核架构的预测调度程序

• DOI: 10.1145/3303084.3309492
• 发表时间: 2019
• 期刊: Proceedings of the 10th International Workshop on Programming Models and Applications for Multicores and Manycores
• 作者: Prodromou, Andreas;Venkat, Ashish;Tullsen, Dean M.
• 通讯作者: Tullsen, Dean M.

Context-Sensitive Fencing: Securing Speculative Execution via Microcode Customization

• DOI: 10.1145/3297858.3304060
• 发表时间: 2019-04
• 期刊: Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems
• 作者: Mohammadkazem Taram;A. Venkat;D. Tullsen