Compiler Optimizations to Exploit Simultaneous Multithreading

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Recently introduced and forthcoming multithreading processor architectures represent new challenges and opportunities for the compilation system.This proposal will focus on three areas, exploiting features of a simultaneous multithreading (SMT) processor:1. Generating Task Threads and Helper Threads - Task-based parallelism provides heterogeneous parallelism that is particularly effective for an SMT processor. Helper threads assist and accelerate the execution of other threads, without necessarily offloading any computation.2. Simultaneous Compilation - Using spare contexts to do dynamic compilation, optimization, and profiling provides the opportunity to perform these functions concurrent with the running program, and continuously, without interrupting other threads.3. Program Placement for SMT - Efficiently using the memory hierarchy is more difficult on an SMT processor because programs interact in non-deterministic ways. Novel code, data, and page placement compiler algorithms will reduce cache misses for multithreaded workloads.This research will involve grad and undergrad students, including students from underrepresented groups, training them in research methodology and practice, and developing particular research expertise. This research will create a compiler and simulation infrastructure that will be made available widely to other academic institutions. This should most benefit institutions that lack resources to develop such an infrastructure themselves.