Self-adaptive Coarse-Grained Reconfigurable Architectures as Reliability Enhancers in Embedded Systems

ARES项目的总体目标是通过自适应错误处理方法开发低成本、可靠的嵌入式系统。在实现总体目标的过程中，我们在项目的前几个阶段开发了基于粗粒度可重构体系结构的错误检测和修复方法。因此，我们创建了整个系统的一个非常可靠和高效的组件，它可以用作底层技术层和上层应用程序层之间的中介。因此，特别适合于自适应跨层错误处理。项目下一阶段的以下三个目标源于这些特点：第一个目标是接入技术层。它旨在调查如何及早检测到技术层上的错误，以及如何将这些错误报告给更高级别的错误以进行纠错。此外，我们计划研究如何在故障出现之前将其检测出来。然后，可以发起直接的对策，以避免在更高的抽象层上的错误行为。我们将使用新的FDSOI技术，该技术提供在运行时改变阈值电压的能力，从而完美地补充了我们的自适应方法。第二个目标是访问应用程序层，以便能够依赖于应用程序使用技术层进行错误处理。第三个目标是开发和生产一种涵盖测试结构的芯片，以定量展示我们在压力条件下的硅胶方法的好处。通过实现这些目标，我们将能够为工业应用和进一步的研究提供一种可靠性方法，以低成本和低能耗提高可靠性，从而为延长CMOS时代提供可能性。

The overall objective of the ARES project is the development of low-cost reliable embedded systems by means of adaptive error handling methods. On the way to our overall goal, we have developed methods for error detection and repair in the previous phases of the project, that are based on coarse grained reconfigurable architectures. Thus, we have created a very reliable and efficient component of the overall system, which can be used as an intermediary between the underlying technological layer and the overlying application layer. Thereby it is particularly suitable for adaptive cross-layer error handling. The following three objectives for the next phase of the project derived from these characteristics: The first goal is to access the technology layer. It is intended to investigate how errors on the technology layer can be detected early, and how these errors can be reported to higher levels for error correction. Furthermore, we plan to investigate how faults can be detected before they emerge. Then direct countermeasures can be initiated to avoid erroneous behavior at a higher abstraction layers. We will use the new FDSOI technology, that provides the ability to change the threshold voltage at run-time and thus complements our adaptive approach perfectly. The second objective is to access the application layer to enable the application-dependent use of the technology layer for error handling. The third objective is the development and production of a chip that covers test structures to demonstrate the benefits of our methodology in silico under stress conditions quantitatively. By achieving these goals, we will be able to provide a reliability methodology for industrial use and also for further research, that increases the reliability at low cost and low energy consumption, and thus offers the possibility to extend the CMOS era.