PERICES-3: Providing Efficient Reliability in Critical Embedded Systems (Phase 3)

芯片制造技术的进步推动了嵌入式系统的惊人增长，嵌入式系统融入了我们的日常生活。然而，这一趋势在设备和系统层面上都面临着严峻的挑战。随着最小特征尺寸的不断缩小，大量的漏洞，如辐射引起的软错误和来自弱单元和工艺变化的间歇性错误，将影响嵌入式和关键系统的健壮性、可靠性和可用性。传统的设计范例假定在设计的整个生命周期内不会失败。即使是用于高端大型机和安全关键应用的经典容错方法，如复制或三模冗余(TMR)，也非常昂贵且仅对非常低的缺陷率有效，因此不适用于嵌入式系统。在这个项目中，我们将开发技术和方法，以非常经济高效的方式确保关键嵌入式系统在硬件和软件层面的健壮性、可靠性、可用性和可恢复性。我们将设计一套技术和工具，用于快速准确地在不同抽象级别进行可靠性建模和估计。我们将提出并发错误检测和定位方法(硬件级)来确保数据完整性。我们还将开发新的恢复机制，从设计级别提供错误定位，并仔细考虑这些机制如何与微体系结构级别和体系结构级别(软件级别)交互。

Improvements in chip manufacturing technology have propelled an astonishing growth of embedded systems which are integrated into our daily lives. However, this trend is facing serious challenges, both at device and system levels. As the minimum feature size continues to shrink, a host of vulnerabilities, such as radiation-induced soft errors and intermittent errors from weak cells and process variations, will influence the robustness, reliability, and availability of embedded and critical systems. The traditional design paradigm assumes no failure during the lifetime a design. Even classical fault tolerant approaches, such as duplication or Triple Modular Redundancy (TMR), which are used for high-end mainframes and safety-critical applications, are very costly and effective only for very small defect rates, and therefore not applicable to embedded systems. In this project we will develop techniques and methodologies to ensure robustness, reliability, availability, and recoverability of critical embedded systems at both the hardware and the software levels in a very cost-effective way. We will design a set of techniques and tools for fast and accurate reliability modeling and estimation at various abstraction levels. We will propose concurrent error detection and localization methods (hardware-level) to ensure data integrity. We will also develop novel recovery mechanisms that provide error localization from the design level, and carefully consider how these interact with both the microarchitectural and architectural levels (software-level).