NeuroTest: Testing Solutions for Neuromorphic Circuits and Architectures

深度神经网络(DNN)在与人工智能和认知处理相关的许多领域中得到了越来越多的关注和应用。由于与使用传统计算架构实现DNN相关的挑战，人们对脑启发的神经形态计算平台和范例越来越感兴趣，以直接并因此更有效地实现DNN。由于神经网络的实现和运算从根本上不同于传统的布尔逻辑，神经形态计算的电路构件和运算模式以及体系结构都带来了新的挑战。从技术角度来看，它们基于新兴的非易失性电阻存储器，这些存储器具有新的制造工艺和步骤，因此容易受到新类型的缺陷和故障的影响。在电路层面，它们使用突触和神经元作为构建块；它们大多是模拟的或包含许多模拟组件(用于存储权重和处理触发功能)，因此模拟组件和数字组件之间没有明显的区别。它们也可能作用于模拟输入，例如尖峰输入，就像尖峰神经网络中使用的那样。非易失性电阻存储器件同时执行存储和逻辑操作(聚合功能)，因此没有明确地将存储和逻辑块分开。从功能的角度来看，与布尔逻辑不同的是，在所有操作周期中，所有输出位都需要正确的数字值，而神经网络具有固有的不准确性和不确定性，这意味着它们具有内在的容错能力。训练和推理两个阶段都是天生不完美的，都包含一些错误。鉴于与传统数字电路和架构相比，神经网络和神经形态实现在技术、电路和功能方面的这些根本挑战，它需要在神经网络和神经形态电路的测试、测试模式生成和为测试而设计(DFT)要求和方法方面采用全新的方法。在神经形态电路按需测试的新哲学中，数字测试和模拟测试、记忆测试和逻辑测试、结构测试和功能测试之间的传统界限已经不复存在。该建议的目的是为神经形态电路和体系结构开发适当的故障模型、测试设计和测试生成方案，以应对这些挑战。

Deep neural networks (DNNs) are gaining increasing attention and usage in many fields related to artificial intelligence and cognitive processing. Due to challenges associated with the implementation of DNNs using traditional computing architectures, there is a growing interest for brain-inspired, aka Neuromorphic computing platforms and paradigms for direct and hence more efficient implementation of DNNs. The building blocks and operation mode of circuitries and the architectures for Neuromorphic computing bring new challenges, since the implementation and operation of neural networks is fundamentally different from traditional Boolean logic. From the technology point of view, they are based on emerging non-volatile resistive memories, which have new fabrication processes and steps, and hence subject to new types of defects and failures. At the circuit-level, they use synapses and neurons as the building blocks; which are mostly analog or contain many analog components (to store weights, and process firing functions) so there is no clear distinction between analog and digital components. They may also work on analog inputs, such as spiking inputs, as used in spiking neural networks. The non-volatile resistive memory devices perform both storage and logical operations (aggregation function), so there is no clear separation of memory storage and logic blocks. From the functional perspective, unlike Boolean logic in which correct digital value of all output bits are required during all operational cycles, neural networks have inherent inaccuracy and non-determinism, which means they have intrinsic tolerance to faults. Both training and inference phases are inherently imperfect and contains some errors. Given these fundamental challenges, in technology, circuitry and functionality of neural networks and neuromorphic implementations compared to traditional digital circuits and architectures, it requires fundamentally new approaches in testing, test pattern generation and Design for Test (DfT) requirements and methods for neural networks and Neuromorphic circuits. In the new philosophy of testing as needed for Neuromorphic circuits, the traditional boundaries between digital and analog test, memory and logic test, structural and functional test do not longer exist. The purpose of this proposal is to develop proper fault models, design for test, and test generation schemes for Neuromorphic circuits and architectures to tackle these challenges.