MRAM Based Design, Test and Reliability for ultra Low Power SoC

微电子工业在未来几年将面临与功耗和能耗相关的重大挑战。静态和动态功耗（已经由泄漏功率主导）将很快开始限制微处理器性能的增长。阻止这一趋势的一个有希望的方法是将非易失性集成为内存缓存的新特性，这将立即将静态功率降至最低，并为正常关闭/即时打开的计算铺平道路。在计算系统的存储器层次结构和逻辑（所谓的逻辑中的存储器）中使用新兴的基于自旋的非易失性存储器设备，即磁性随机存取存储器（MRAM），为低功耗系统提供了巨大的机会。本研究项目的目标是调查、设计、开发和分析混合CMOS- mram正常关闭计算架构，其中mram与传统CMOS器件和存储器一起用于不同级别的存储器层次（逻辑存储器、寄存器文件、不同级别的缓存、主存储器），以实现超低功耗，提供高性能和低成本。我们计划通过涵盖单元、阵列、存储器层次结构和体系结构设计以及故障建模、测试设计、可靠性和健壮性的各个方面来突出该技术的全部潜力。我们还将开发一套从电路到系统级别的建模，设计和仿真工具，以设计和评估混合存储器层次结构和处理器架构。

The microelectronics industry will face major challenges related to power dissipation and energy consumption in the next years. Both static and dynamic consumption (already dominated by the leakage power) will soon start to limit microprocessor performance growth. A promising way to stop this trend is the integration of non-volatility as a new feature of memory caches, which would immediately minimize static power as well as paving the way towards normally-off/instant-on computing. The use of emerging spin-based non-volatile memory devices, aka Magnetic Random Access Memory (MRAM), in both memory hierarchy and logic (the so called memory-in-logic) of computing systems provides a huge opportunity for low-power systems. The objective of this research project is to investigate, design, develop, and analyze hybrid CMOS-MRAM normally-off computing architectures in which MRAMs are used at various levels of the memory hierarchy (memory-in-logic, register files, different levels of cache, main memory) along with traditional CMOS devices and memories to achieve ultra-low-power and provide high performance and low cost. We plan to highlight the full potential of this technology by covering various aspects of the cell, array, memory hierarchy, and architecture design as well as fault modeling, design for test, reliability, and robustness. We will also develop a set of modeling, design, and simulation tools from circuit to system levels to design and evaluate hybrid memory hierarchies and processor architecture.