CPA-DA: Dealing with Voltage Variations and Supply Noise During Performance Verification in Nanometer Tehcnology Designs

提案ID：0811632，PI名称：Mohammad特赫拉尼利普，PI机构：康涅狄格大学，标题：CPA-DA：在纳米技术设计中的性能验证期间处理电压变化和电源噪声摘要：电源噪声将是纳米技术设计中的一个严重问题，特别是在后硅性能验证和速度绑定期间。必须有效地考虑这种影响，因为它给芯片制造商/铸造厂带来了设计、测试和可靠性方面的挑战。随着电源电压的降低和阈值电压进一步降低的限制，这种情况变得更加复杂，从而降低了噪声容限和提高了电路灵敏度。该项目需要新的全面和高效的PSN分析、功率模型、模式生成和可测试性设计(DFT)方法，以缓解新技术世代中性能验证和速度入库过程中的上述问题。该项目还将解决功率分析的实际问题，并提出新的功率模型、统计PSN分析和有效的测量程序，以测量由于过高的电压、工艺和环境变化而导致的性能下降。这项研究的智力价值在于它将显著提高芯片的质量和可靠性，降低制造成本。更广泛的影响是(I)对EDA和半导体行业的调试和诊断小组的贡献，以评估和验证设计原型的性能，(Ii)本科生和研究生的教育，以及(Iii)新课程的开发，以及(Iv)向学术界和工业界的研究人员传播数据和方法。

Proposal ID: 0811632, PI Name: Mohammad Tehranipoor, PI Institution: University of Connecticut, Title: CPA-DA: Dealing with Voltage Variations and Supply Noise During Performance Verification in Nanometer Technology DesignsABSTRACT: Power supply noise (PSN) will be a serious issue in nanometer technology designs especially during post-silicon performance verification and speed binning. Such effect must be efficiently taken into consideration, as it poses design, test and reliability challenges for the chip manufacturers/foundries. This situation has grown more complicated with reducing supply voltage and the limitation of further reduction of threshold voltage leading to reduced noise margin and increased circuit sensitivity. This project addresses the necessity of new comprehensive and efficient PSN analysis, power model, pattern generation, and design for testability (DFT) methods to alleviate the above issues during performance verification and speed binning in new technology generations. This project will also address the practical issues of power analysis and proposes new power model, statistical PSN analysis, and efficient measurement procedure for measuring performance degradation due to excessive voltage, process and environmental variations. The Intellectual Merit of the research is that it will significantly increase the quality and reliability of chips and reduce the manufacturing costs. The broader impact is (i) the contribution to debugging and diagnostic groups of EDA and semiconductor industry to assess and verify the performance of design prototypes, (ii) the education of undergraduate and graduate students, and (iii) the development of new courses, and (iv) the dissemination of data and methodologies to researchers in academia and industry.