CPA-CSA-T: Arsenal: Extending Moore's Law through the Design, Synthesis and Use of Massively Heterogeneous Systems

对功耗和微架构可伸缩性的关注促使最近的工业向多核处理器过渡。在不久的将来，由于超大规模集成电路的规模限制，处理器将只能利用一小部分的模具在同一时间全速。三维CMOS集成的出现通过实质上增加器件数量而没有改善晶体管功率效率而加剧了这个问题。这种“利用率墙”有可能阻止摩尔定律的发展，并阻止处理器性能的年度改进，这些改进在过去40年中改变了社会。本研究通过检查阿森纳处理器的设计、构造和分析来攻击利用墙。Arsenal处理器由10到100甚至1000个专用处理元件（SPE）组成的异构阵列组成，其中一小部分将随时处于活动状态。Arsenal系统中的SPE将从专用ASIC到图形加速器和无序超标量不等。程序的不同部分将在最适合每个部分的SPE上运行。由于专用处理器通常更小，效率更高，每个程序只使用一小部分芯片，但效率极高。我们的初步结果表明，阿森纳的设计提高了高达7倍的功率效率相比，不太积极的异构方法。虽然阿森纳式处理器的潜在好处是诱人的，但阿森纳系统也带来了重大挑战。设计人员必须找到一种快速开发各种SPE的方法，这些SPE可以共同提高典型最终用户工作负载的效率。阿森纳设计中的内存系统必须为每个SPE提供足够的内存带宽，阿森纳处理器必须包括一个能够支持数千个SPE通信的片上互连。为此，我们将与麻省理工学院ATAC项目合作，该项目专注于片上互连设计，我们将把他们的互连纳入我们自己的工作中。拟议的工作将探讨在设计具有潜在的1000个专用核心的大规模异构阿森纳系统时出现的许多架构挑战。其目标是展示阿森纳处理器的潜力，开发设计完整的阿森纳系统所需的工具，并建立一个完整的，通用的原型阿森纳处理器。

Power and microarchitectural scalability concerns have motivated the recent industrial transition to multicore processors. In the near future, because of VLSI scaling limitations, processors will only be able to make use of a small fraction of the die at one time at full speed. The emergence of three-dimensional CMOS integration exacerbates this problem by substantially increasing device count without improving transistor power efficiency. This "utilization wall" threatens to halt the progress of Moore's law and stop the yearly improvements in processor performance that have transformed society over the last 40 years. This research attacks the utilization wall by examining the design, construction and analysis of Arsenal processors. Arsenal processors are comprised of a heterogeneous array of 10s to 100s to even 1000s of specialized processing elements (SPEs), a small subset of which will be active at any time. The SPEs in an Arsenal system will vary from specialized ASICs to graphics accelerators and out-of-order superscalars. Different parts of a program will run on the SPEs best suited to each part. Since specialized processors are generally smaller and more efficient, each program will use just a fraction of the die, but will do so extremely efficiently. Our preliminary results show that Arsenal designs improve power efficiency by up to 7x compared to less aggressively heterogeneous approaches. While the potential benefits of Arsenal-style processors are alluring, Arsenal systems present significant challenges as well. Designers must find a way to quickly develop a wide range of SPEs that can collectively improve efficiency for a typical end-user's workload. The memory system in an Arsenal design must deliver sufficient memory bandwidth to each SPE.Arsenal processors must include an on-chip interconnect that can support thousands of communicating SPEs. To this end, we will colloborate with the MIT ATAC project, which focuses on on-chip interconnect design, and we will incorporate their interconnect into our own work. The proposed work will explore many architectural challenges that arise in designing massively heterogeneous Arsenal systems with potentially 1000s of specialized cores. Its goals are to demonstrate the potential of Arsenal processors, develop the tools needed to design complete Arsenal-based systems, and to build a complete, general-purpose prototype Arsenal processor.