EMT/MISC: Theory and methods for design and synthesis of approximate logic circuits and systems: a paradigm for emerging technologies

摘要本研究开发了一种全新的自动合成和人工设计数字电路的方法，以实现近似但可接受的逻辑功能版本。这种方法为许多广泛使用的数字系统提供了成本更低、速度更快的版本。这项研究的好处将随着每一项新的纳米技术的采用而增长。所有未来的纳米级CMOS和新兴的非CMOS纳米技术都将面临越来越多的非理想性问题。特别是高工艺变化，缺陷密度和噪声敏感性。这些非理想性带来了一个根本性的挑战，因为如果不加以控制，它们将侵蚀采用这些纳米技术所带来的大部分好处。这项研究涉及到近似设计和合成的发展，这是一个全新的范式来处理这一根本性的挑战。这个范例建立在最近的一项论证之上，该论证表明，对于广泛的数字系统类别，行为规范具有相当大的灵活性。规范中的这种灵活性以可接受的偏离名义行为规范的形式被捕获，并且开发了第一个逻辑综合和设计方法和工具来利用这些偏离来降低成本或提高性能和产量。与所有现有的研究方向相比，该范式通过简化设计电路来减轻非理想性的影响。这种方法适用于许多嵌入式系统的特定应用芯片和许多类型的广泛使用的处理器，例如算术协处理器、数字信号处理处理器和图形处理器。总的来说，受益于这种方法的芯片构成了任何一年销售的所有芯片的很大一部分。这项研究为大幅度提高未来纳米技术的成本、性能和产量开辟了一条全新的途径

AbstractThis research develops a completely new approach for automatically synthesizing and manually designing digital circuits that implement approximate-yet-acceptable versions of logic functions. This approach provides lower cost and higher speed versions of many widely used digital systems. The benefits of this research will grow with the adoption of each new nanotechnology.All future nanoscale CMOS and emerging non-CMOS nanotechnologies will suffer from increasing levels of non-idealities ? especially high process variations, defect densities, and noise sensitivity. These non-idealities present a fundamental challenge, since, if left unchecked, they will erode most benefits provided by adoption of these nanotechnologies. This research involves development of approximate design and synthesis, a completely new paradigm for dealing with this fundamental challenge. This paradigm builds upon the recent demonstration that there is considerable flexibility in the behavioral specifications for wide classes of digital systems. Such flexibilities in specifications are captured in the form of acceptable deviations from the nominal behavioral specifications and the first logic synthesis and design approaches and tools are developed to exploit these deviations to reduce cost or enhance performance and yield. In contrast to all existing research directions, this paradigm mitigates the effects of non-idealities by simplifying the designed circuit. This approach is applicable to application-specific chips for many embedded systems and many types of widely used processors, e.g., arithmetic co-processors, processors for digital signal processing, and graphics processors. Collectively, the set of chips that benefit from this approach constitute a significant proportion of all chips sold in any given year. This research opens a completely new avenue for dramatically improving cost, performance, and yield for future nanotechnologies.1