Optimization of Test and Diagnosis Infrastructure for Multicore Chips

CCF-0903392多核芯片测试和诊断基础架构的优化Krishnendu Duke University Chakrabarty摘要多核集成电路的出现通过处理器、图形加速器、存储器和其他类型内核的芯片上集成，提供了计算领域的持续技术进步。需要测试解决方案来降低成本和缺陷逃逸，并通过诊断来促进修复和重新配置。因此，该项目针对的是全面缺陷筛选的新方法、测试交付的优化技术以及快速识别故障岩芯的诊断流程。它围绕以下主题构建：(I)生成高质量测试以增强核心级模式，包括电源管理结构和时钟域边界的测试，以及互连结构和到核心的接口的测试；(Ii)用于利用互连结构进行测试数据传输的理论和优化工具；(Iii)减少识别故障核心和时钟域所需时间的优化方法。该项目是与英特尔和AMD的合作伙伴合作进行的。该项目将降低测试成本和缺陷级别，并为基于多核的系统带来更高的出厂产品质量。测试基础设施将通过使用备用核心促进现场测试、诊断和动态重新配置。由此给社会带来的好处包括为广泛的应用提供更便宜和可靠的计算平台。本科生和研究生将为半导体行业做好准备。SRC硕士-S奖学金和博士奖学金将被用作招聘工具，特别是对代表性不足的群体。在IEEE/ACM全球分会的会议和讲座上的教程将导致研究成果的广泛传播。

CCF - 0903392 Optimization of Test and Diagnosis Infrastructure for Multicore ChipsChakrabarty, Krishnendu Duke University ABSTRACTThe emergence of multicore integrated circuits offers continued technological advances in computing through the on-chip integration of processors, graphics accelerators, memories, and other types of cores. Test solutions are needed to reduce cost and defect escapes, and to facilitate repair and reconfiguration through diagnosis. This project is therefore directed at new methods for comprehensive defect screening, optimization techniques for test delivery, and diagnosis flows to quickly identify faulty cores. It is structured around the following topics: (i) generation of high-quality tests to augment core-level patterns, including tests for power-management structures and clock-domain boundaries, and tests for the interconnect fabric and interfaces to the cores; (ii) theory and optimization tools for utilizing the interconnection fabric for test-data transportation; (iii) optimization methods to reduce the time needed for identifying faulty cores and clock domains. The project is being carried out in collaboration with partners at Intel and AMD.This project will reduce test cost and defect levels, and lead to higher shipped-product quality for multicore-based systems. The test infrastructure will facilitate in-field testing, diagnosis, and dynamic reconfiguration through the use of spare cores. Resulting benefits for society include cheaper and reliable computing platforms for a wide range of applications. Undergraduate and graduate students will be prepared for the semiconductor industry. SRC Master?s Scholarships and PhD Fellowships will be used as recruitment tools, especially for under-represented groups. Tutorials at conferences and lectures at IEEE/ACM Chapters worldwide will lead to broad dissemination of research results.