SHF: Small: Collaborative Research: Fast Sign-Off of Nanoscale Memory: From Predictive Device Modeling to Statistical Circuit Synthesis

在22nm及以下节点上，过多的工艺变化和可靠性下降极大地挑战了片上存储器的扩展。在目前的实践中，为了在所有工艺、电压和温度条件下达到预期的性能，通常需要对测试硅进行完全定制设计和广泛的实验。尽管如此昂贵的方法在今天是可以接受的？S芯片设计，它大大降低了设计的生产率和可预测性。当不断增加的变化缩小了设计窗口并加剧了内存设计的复杂性时，情况变得更加严重。该提案旨在开发创新的方法，通过预测可变性模型、统计抽样方案、稳健的优化算法和高效的硅表征技术的无缝集成，在硅路线图的末端及以后实现片上存储器的快速签名。此外，这些新成果将整合到一个在线框架中，以统计基准后si存储器设计，有助于说明10nm节点以外存储器设计的各种机会。这项研究工作将促进对不可靠组件的可靠设计的基础研究，提高广泛应用的设计生产力，并加快新兴纳米电子器件的统计设计解决方案。此外，通过新颖的教育课程和基于网络的传播工具，该项目将把新开发的设计知识传递给不同的学生群体，他们将领导未来从计算、通信到消费电子等所有类型的纳米级集成系统的创建。

The scaling of on-chip memory is tremendously challenged by the excessive amount of process variations and reliability degradation at the 22nm node and below. In current practice, full custom design and extensive experimentation on test silicon are often necessary to achieve the desired performance under all process, voltage, and temperature conditions. Although such an expensive approach is acceptable in today?s chip design, it drastically reduces design productivity and predictability. The situation becomes even more severe when the ever-increasing nature of variations narrows the design window and exacerbates memory design complexity. This proposal aims to develop innovative methodologies that will enable fast sign-off of on-chip memory at the end of the silicon roadmap and beyond, through the seamless integration of predictive variability models, statistical sampling schemes, robust optimization algorithms, and efficient silicon characterization techniques. Furthermore, these new outcomes will be integrated into an online framework to statistically benchmark post-Si memory design, helping illustrate the diverse opportunities of memory design beyond the 10nm node. This research effort will facilitate fundamental research on reliable design with unreliable components, enhance design productivity for a wide range of applications, and expedite statistical design solution for emerging nanoelectronic devices. In addition, through novel education curricula and web-based dissemination tools, this project will transfer the newly developed design knowledge to a diverse population of students, who will lead the creation of future nanoscale integrated systems of all types, from computation, communication, to consumer electronics.