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SHF: Small: Towards a Versatile Analytical Modeling Toolset for Evaluating Memory Hierarchy Design

SHF: Small: Towards a Versatile Analytical Modeling Toolset for Evaluating Memory Hierarchy Design
SHF:小型:用于评估内存层次结构设计的多功能分析建模工具集
批准号:
1116540
负责人:
Yan Solihin
金额:
$40.0万
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
2011
资助国家:
美国
项目状态:
已结题
起止时间:
2011-08-01 至 2015-07-31

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中文摘要
翻译
今天,用于评估未来计算机系统设计的主要工具是仿真,其中每个机器指令及其对处理器和存储器状态的影响都进行了详细的仿真。虽然功能强大且用途广泛,但处理器模拟非常慢:大约比本地执行慢四到五个数量级。在未来,由于硬件和软件系统的复杂性以及工作负载的多样性的同时增加,仅仅依靠处理器仿真将受到太多的限制。分析建模试图捕捉设计的各种参数之间的基本关系,并捕捉它们如何影响性能或功耗/能耗。分析模型的运行速度要快得多,并且可以相当准确。不幸的是,分析模型的广泛使用受到了研究人员可以使用和构建的广泛可用的工具集的缺乏以及使用和开发它们的高门槛的阻碍。这个建议的目的是将各种不同的分析模型集成到一个单一的工具集,可用于计算机体系结构设计和评估的研究人员。这个项目的预期成果是一个工具,通过三个重要的角色,帮助处理器模拟:提供能力的原因是什么参数决定的结果的性能现象,发现洞察架构参数如何从根本上相互关联,并提供一阶近似,允许缩小搜索空间的模拟研究。该项目使计算机设计和评估在质量(可以获得更深入的见解)和资源效率(获得相同的观察结果所需的模拟时间更少)方面得到显着改善。该项目的交付成果包括一个工具集,该工具集将项目的组件集成到一个易于使用并具有智能界面的软件包中,以及适合本科生和研究生课程的课堂材料。这些材料将可供公众下载,社区增强和社区扩展。
英文摘要
Today, the primary tool used for evaluating future computer system designs is simulation, where each machine instruction and its impact on processor and memory state are simulated in great details. While powerful and versatile, processor simulation is exceedingly slow: roughly four to five orders of magnitude slower than native execution. In the future, solely relying on processor simulation will be too constraining, due to simultaneous increase in the complexity of hardware and software systems, and variety of workloads. Analytical modeling is an attempt to capture fundamental relationships between various parameters of a design and to capture how they affect performance or power/energy consumption. An analytical model is much faster to run and can be reasonably accurate. Unfortunately, widespread uses of analytical models have been hampered by the lack of widely available toolset that researchers can use and build upon, and the high barrier of entry into using and developing them. The objective of this proposal is to integrate various disparate analytical models into a single toolset that can be used by researchers for computer architecture design and evaluation. The expected outcome of this project is a tool that aids processor simulation through three important roles: providing ability to reason about what parameters determine the outcome of a performance phenomenon, discovering insights into how architecture parameters fundamentally relate to one another, and providing first-order approximation that allows narrowing down the search space for simulation studies. The project enables computer design and evaluation to be improved significantly in terms of quality (deeper insights can be obtained), as well as resource efficiency (less simulation time is required to arrive at the same observations). A deliverable of the project includes a toolset that integrates components of the project into a software package that is easy-to-use and has intelligent interface, and classroom materials suitable for undergraduate and graduate courses. These materials will be made available for public download, community enhancement, and community extension.
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会议论文
Collaborative Research: CSR: Medium: Scaling Secure Serverless Computing on Heterogeneous Datacenters
Collaborative Research: CNS Core: Medium: Understanding and Strengthening Memory Security for Non-Volatile Memory
Collaborative Research: PPoSS: Planning: Scaling Secure Serverless Computing on Hetergeneous Datacenters
SHF: Small: Collaborative Research: Efficient Memory Persistency for GPUs
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