SHF: Small:Scalable Support for Concurrency in Multicore Systems

预计处理器设计将继续众核趋势，通常具有异构计算组件。虽然原始计算能力可能会随着核心数量的增加而大致线性增长，但不幸的是，在应用程序级别实现可用的计算能力仍然是一个挑战。CPU和内存速度之间的差距继续扩大，导致内存系统经常无法满足计算需求。并行应用程序开发人员和用户都必须了解底层硬件和运行时的详细信息，以便从系统中获得最大的好处，从而降低性能可移植性。程序员也越来越多地通过使用预并行库来利用并发性，导致可组合性差。该研究旨在通过提高多核和多处理器系统的易用性、可扩展性和能源效率来解决这些问题，并对从智能手机到服务器的环境产生影响。利用的关键观察结果是高级模块化应用程序结构具有可预测的空间局部性。不是如在当前设计中那样对该高速缓存线粒度使用刚性参数，而是底层高速缓存设计适应于匹配现有访问粒度。此外，本研究旨在开发运行时技术，通过a）尊重任务之间的依赖关系，B）匹配任务需求与资源的计算和内存能力，以及c）确定在每个级别的适当程度的并行性，以最大限度地减少执行时间和能源消耗的应用程序任务映射到硬件计算资源。新的存储器系统设计将提高片上存储利用率，消除传输未使用的数据字节所浪费的能量，并减少片外存储器带宽的压力。新的运行时技术将提高易用性和可扩展性的计算利用率的日益创新的应用程序的未来。

Processor designs are predicted to continue the many-core trend, often with heterogeneous computational components. While the raw compute power may increase roughly linearly with the core count, unfortunately, realizing the available computational power at the application level remains a challenge. The gap between CPU and memory speeds continues to widen, resulting in the memory system often being unable to feed the computational demands. Parallel application developers and users alike must be aware of the details of the underlying hardware and runtime details in order to extract the most benefit from the system, compromising performance portability. Programmers are also increasingly exploiting concurrency via the use of pre-parallelized libraries, resulting in poor composability. The proposed research aims to address these issues by improving the ease of use, scalability, and energy efficiency of multicore and multiprocessor systems, with impact on environments ranging from smart phone to servers.As part of this research, a "pay-as-you-use" application-adaptive approach is used to develop a novel on-chip memory system. The key observation leveraged is that high-level modular application structure has predictable spatial locality. Rather than use a rigid parameter for the cache line granularity as in current designs, the underlying cache design adapts to match existing access granularity. Additionally, this research aims to develop runtime techniques that map application tasks to hardware compute resources by a) respecting the dependencies across tasks, b) matching task needs with the computational and memory capabilities of the resource, and c) determining the appropriate degree of parallelism at each level to minimize execution time and energy consumption. The new memory system design will improve on-chip storage utilization, eliminate energy wasted in transferring unused bytes of data, and reduce the pressure on off-chip memory bandwidth. The new runtime techniques will improve the ease of use and scalability of computational utilization by the increasingly innovative applications of the future.