SHF:Small:Graph Sparsification Approach to Scalable Parallel SPICE-Accurate Simulation of Post-layout Integrated Circuits

与传统的快速SPICE仿真技术不同，传统的快速SPICE仿真技术依赖于各种近似方法来权衡仿真精度以获得更高的速度，SPICE精确的集成电路（IC）仿真可以真实地预测电路的电气行为，因此在纳米级集成电路的设计和验证中不可或缺。然而，对于布局后的纳米级电路，使用传统的spice精确模拟技术来封装通过复杂寄生耦合的数百万甚至数十亿器件可能会非常昂贵，因此不适用于大型IC设计，因为使用直接求解方法解决大型稀疏矩阵问题的运行时间和内存成本将随着电路尺寸和寄生密度的增加而迅速增加。为了提高布局后仿真的效率和能力，最近提出了预先条件迭代求解技术来代替直接求解方法。然而，现有的布局后电路仿真的预条件方法通常对待分析电路和系统进行了各种假设和约束，因此无法有效可靠地应用于通用spice精确电路仿真。在这个研究项目中，PI将利用最近的图稀疏化研究，研究有效而稳健的面向电路的预处理方法，用于可扩展的spice精确后布局IC模拟。通过系统地稀疏化由密集寄生元件和布局后电路的复杂器件元件产生的线性/非线性动态网络，PI将研究和开发可扩展的，更重要的是，可并行的预置迭代算法，从而在时间和频域上为spice精确的IC模拟提供更高的速度和容量。这项工作的成功完成将立即使半导体行业受益。通过该项目开发的算法和方法将整合到本科/研究生水平的VLSI设计/CAD课程中，而研究结果将广泛传播给主要的半导体和EDA公司，以供潜在的工业应用。根据这项研究计划开发的CAD工具亦会与合作的工业伙伴交换。在拟议的研究计划中获得的经验也可能有助于其他科学和工程领域的计算进步，影响与大型/复杂系统建模和仿真相关的更广泛的研究领域。

Unlike traditional fast SPICE simulation techniques that rely on a variety of approximation approaches to trade off simulation accuracy for greater speed, SPICE-accurate integrated circuit (IC) simulations can truthfully predict circuit electrical behaviors, and therefore become indispensable for design and verification of nanoscale ICs. However, for post-layout nanoscale circuits, using traditional SPICE-accurate simulation techniques to encapsulate multi-million or even multi-billion devices coupled through complex parasitics can be prohibitively expensive, and thus not applicable to large IC designs, since the runtime and memory cost for solving large sparse matrix problems using direct solution methods will increase quickly with the growing circuit sizes and parasitics densities. To achieve greater simulation efficiency and capacity during post-layout simulations, preconditioned iterative solution techniques have been recently proposed to substitute the direct solution methods. However, existing preconditioned methods for post-layout circuit simulations are typically designed with various assumptions and constraints on the circuit and systems to be analyzed, which therefore cannot be effectively and reliably applied to general-purpose SPICE-accurate circuit simulations. In this research project, the PI will study efficient yet robust circuit-oriented preconditioning approaches for scalable SPICE-accurate post-layout IC simulations by leveraging recent graph sparsification research. By systematically sparsifying linear/nonlinear dynamic networks originated from dense parasitics components and complex device elements of post-layout circuits, scalable, and more importantly, parallelizable preconditioned iterative algorithms will be investigated and developed by the PI to enable much greater speed and capacity for SPICE-accurate IC simulations in both time and frequency domains.The successful completion of this work will immediately benefit the semiconductor industries. The algorithms and methodologies to be developed through this project will be integrated into undergraduate/graduate level VLSI design/CAD courses, while the research results will be broadly disseminated to major semiconductor and EDA companies for potential industrial applications. The CAD tools developed under this research plan will also be exchanged with collaborating industrial partners. The acquired experience in the proposed research plan is also likely to contribute to computing advances in other science and engineering fields, impacting broader research areas that are related to large/complex system modeling and simulation.