SHF: Small: Dynamic Power Management in the Dark Silicon Era

未来的异构多核微处理器预计会受到功率限制，因此并非所有晶体管都能同时通电。当功率被转移到加速器时，通用核心将需要灵活地适应严重受限的功率分配，反之亦然。此外，随着多核架构变得更加异构化，线程到核心的能量感知调度正变得势在必行。本研究开发了功率门控多核架构和集成调度和功率分配算法，以最大限度地提高分配功率的变化和潜在的严格限制。研究的一个方面是设计、综合和评估功率门控通用和数据并行加速器微架构，这些微架构由可配置通道组成——通过管道的水平切片——允许每个核心针对应用程序进行动态剪裁。目标是演示可容忍的性能和电源门控开销，以及适应工作负载行为的灵活性。这项工作的第二个方面是一种新的优化方法，该方法可以有效地找到线程和线程到核分配的接近全局最优配置，而不需要离线培训或预先了解工作负载。该方法结合了减少采样技术，响应面模型对在线优化的适应，有限的在线分析信息的结合，以及启发式在线搜索。该研究将提高未来严重功率受限设备的计算能力；招收本科、研究生和/或博士后女性工程师；并被纳入计算机体系结构和启发式优化类。

Future heterogeneous multicore microprocessors are expected to be sopower constrained that not all transistors will be able to be poweredon at once. The general-purpose cores will be required to nimblyadapt to severely constrained power allocations when power is divertedto accelerators, and vice versa. In addition, energy-aware schedulingof threads to cores is becoming imperative as multicore architecturesbecome more heterogeneous. This research develops power gatedmulticore architectures and integrated scheduling and power allocationalgorithms for maximizing throughput given varying and potentiallystringent limits on allocated power.One facet of the research is the design, synthesis, and evaluation ofpower gated general-purpose and data-parallel acceleratormicroarchitectures comprised of deconfigurable lanes--horizontalslices through the pipeline--that permit dynamic tailoring of eachcore to the application. The goal is to demonstrate tolerableperformance and power-gating overheads yet flexibility in adapting toworkload behaviors. A second aspect of the work is a new optimizationapproach that efficiently finds a near-global-optimum configuration oflanes and thread-to-core assignment without requiring offline trainingor foreknowledge of the workload. The approach combines reducedsampling techniques, adaptation of response surface models to onlineoptimization, incorporation of limited online profiling information,and heuristic online search. The research will improve thecomputational capability of future severely power-constrained devices;involve undergraduate, graduate, and/or postdoc women engineers; andbe incorporated into computer architecture and heuristic optimizationclasses.