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CSR: Small: A Time-Predictable Integrated CPU-GPU Architecture for Hard Real-Time Systems

CSR: Small: A Time-Predictable Integrated CPU-GPU Architecture for Hard Real-Time Systems
CSR:小型:用于硬实时系统的时间可预测集成 CPU-GPU 架构
批准号:
1421577
负责人:
Wei Zhang
金额:
$50.0万
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
2014
资助国家:
美国
项目状态:
已结题
起止时间:
2014-10-01 至 2019-09-30

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中文摘要
翻译
大规模和节能的计算能力,加上增强的可编程性,使图形处理单元(GPU)成为加速各种数据密集型硬实时应用的理想平台,如医疗数据处理,自主自动导航和基于视觉的飞机控制。计算机行业已经为嵌入式计算应用提供了几种GPU。然而,这些GPU都不能保证时间的可预测性,这对于硬实时系统至关重要。将CPU和GPU集成在同一个芯片上,使得实现时间可预测性更具挑战性。 本项目的目标是通过研究时间可预测的CPU-GPU集成架构的设计来满足这一需求,该架构也可以提供高性能和高能效。本项目通过以下方式解决这一问题:(i)系统地分析和评估GPU和CPU-GPU集成架构的时间不可预测性;(ii)探索用于集成CPU-GPU的时间可预测和异构末级高速缓存(LLC)架构,包括私有、分区和锁定LLC;(iii)设计时间可预测和异构的片上互连网络,可以有效地支持CPU和GPU内部和之间的通信;(iv)设计时间可预测的存储器控制器,以实现可扩展、安全和紧密的WCET(最坏情况执行时间)估计;(v)为建议的集成CPU-GPU处理器开发第一个WCET分析器,以支持硬实时计算。 其他项目活动包括努力将研究成果转化为产业,将与研究有关的主题和项目纳入课程,以及开放源码软件的分发。
英文摘要
Massive and energy-efficient computation capability, coupled with the enhanced programmability, makes Graphics Processing Units (GPUs) a desirable platform to accelerate a variety of data-intensive hard real-time applications such as medical data processing, autonomous auto navigation, and vision-based aircraft controls. The computer industry has already delivered several GPUs for embedded computing applications. However, none of these GPUs can guarantee time predictability, which is crucial for hard real-time systems. The integration of the CPU and the GPU on the same die makes it even more challenging to attain time predictability. The goal of this project is to fill this need, though investigation of the design of time-predictable integrated CPU-GPU architectures that can also offer high performance and energy efficiency.The project addresses this problem by: (i) systematic analysis and evaluation of time-unpredictability of GPUs and integrated CPU-GPUs; (ii) exploration of time-predictable and heterogeneous last-level cache (LLC) architectures for integrated CPU-GPUs, including private, partitioned, and locked LLCs; (iii) design of time-predictable and heterogeneous on-chip interconnection networks that can efficiently support communications within and across the CPUs and GPU; (iv) design of time-predictable memory controllers to enable scalable, safe, and tight WCET (Worst-Case Execution Time) estimation; (v) development of the first WCET analyzer for the proposed integrated CPU-GPU processor to support hard real-time computing. Other project activities include efforts to transition the results of the research to industry, integration of topics and projects related to the research in courses, and open-source distribution of software.
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