SHF: Small: Synthesis of Robust Clock Networks for Multiple-Corner Multiple-Mode Designs

通常在移动和便携式设备中发现的功率敏感电子产品的集成电路通常在几种工作模式下工作，以便在保持能源效率的同时提供足够的性能。即使在制造过程和操作环境注入的不确定性下，这些电路也必须健壮地运行。这种复杂电路或系统的操作由一个网络同步，该网络向电路或系统的各个组件提供时钟信号。这项研究的成功将导致高度可扩展的合成工具，可以胜任地设计强大的时钟网络，以同步移动应用的大规模高复杂性集成电路。夏令营活动和社区外展活动将嵌入电路、系统和计算机相关的基本概念，使K-12学生受益，并扩大代表性不足的学生参与计算机工程。通过将研究成果整合到本科和研究生课程中，学生将在电路、数值线性代数和基本算法等领域获得广泛的技能训练。现有的合成鲁棒时钟系统的方法包括应用迭代的合法化步骤来纠正不同操作场景下初始时钟网络的时间违规。与这样一个冗长的迭代过程相比，它不能保证收敛到一个可行的解决方案，在这个项目中将开发一种构造正确的方法。提出的研究活动是由可重构电路结构驱动的，该电路结构可以在考虑制造过程和操作环境的不同角落的同时，在不同的操作模式下稳健地传递时钟信号。本课程将探讨在不同运作情况下，如何安排时钟讯号在不同电路元件到达时间的基本问题。将开发各种将安全裕度插入可重构电路结构的技术。对于一些关键组件，将插入冗余路径，以便在冗余路径之一发生故障时，可以将同步信号健壮地传递给它们。一套用于各种基准测试目的的新电路也将提供，以促进这一重要领域的研究。

Integrated circuits for power-conscious electronics commonly found in mobile and portable devices typically operate in several operational modes in order to deliver adequate performance while maintaining energy efficiency. These circuits also have to operate robustly even under uncertainties injected by the manufacturing process and operating environments. The operation of such a complex circuit or system is synchronized by a network that delivers a clocking signal to various components of the circuit or system. Success in this research will lead to highly scalable synthesis tools that can competently design robust clock networks to synchronize large-scale high-complexity integrated circuits for mobile applications. Summer camp activities and community outreach activities that embed essential concepts related to circuits, systems and computing will be developed, benefiting K-12 students and broadening the participation of underrepresented students in computer engineering. With the integration of research results into the undergraduate and graduate curricula, students will be trained with a broad range of skills, in areas such as circuits, numerical linear algebra, and fundamental algorithms.The existing approaches of synthesizing a robust clocking system involve the application of iterations of legalization steps to correct the timing violations of an initial clock network in different operating scenarios. In contrast to such a lengthy iterative process that has no guarantee of convergence to a feasible solution, a correct-by-construction approach will be developed in this project. The proposed research activities are driven by a reconfigurable circuit structure that could robustly deliver the clocking signal for different modes of operation, while accounting for different corners of manufacturing process and operating environments. The fundamental problems of scheduling the arrival times of clocking signals at different components of a circuit under various operating scenarios will be explored. Various techniques of inserting safety margins into the reconfigurable circuit structure will be developed. For some critical components, redundant paths will be inserted such that the synchronizing signal could be delivered to them robustly should a failure occur in one of the redundant paths. A new suite of circuits for various benchmarking purposes will also be made available to promote research in this important area.