SHF: Small: Bridging the Gap Between Global and Detailed Routing of Integrated Circuits

随着半导体技术进入亚10 nm时代，集成电路(IC)的计算机辅助设计(CAD)变得非常复杂。今天的设计者必须处理由制造设施强加的日益复杂的规则，以确保芯片能够成功制造。该项目旨在开发CAD工具，将主要设计规则纳入设计流程的关键、更高阶段，即全局布线阶段。通过将这些规则集成到全局布线中，该项目旨在加快亚10纳米制度下的IC设计进度。该项目的其他更广泛的目标包括：公开发布为促进学术研究而开发的工具的版本，向主要半导体公司转让技术，与密歇根大学麦迪逊分校现有的两门课程整合，以及培训研究生和本科生以获得当今IC-CAD就业市场所需的技能。该项目的任务集中在研究全球布线抽象级别的设计规则感知模型，包括用于更好地进行引脚访问规划的机器学习技术。此外，该项目将确定现代设计规则造成的新的路线选择挑战，并将研究适当的优化战略，包括基于图表和数学编程技术，以解决这些挑战。

As semiconductor technology enters the sub-10nm era, it has significantly complicated the computer-aided design (CAD) of integrated circuits (ICs). Today's designer must deal with increasingly complex rules, imposed by the manufacturing facility so as to ensure that the chip can be successfully fabricated. This project aims to develop CAD tools that incorporate major design rules within a key, higher stage of the design flow, namely the global routing stage. By integrating these rules into global routing, the project aims to accelerate the progress of IC design within the sub-10nm regime. Other broader goals of the project include: public release of a version of the tools developed to facilitate academic research, technology transfer to major semiconductor companies, integration with two existing courses at UW-Madison, and training graduate and undergraduate students to gain the necessary skills for today's IC-CAD job market.The project tasks are centered around investigating design-rule-aware models at the global routing level of abstraction, including machine-learning techniques for better pin-access planning. In addition, the project will identify new routing challenges caused by modern design rules and will investigate appropriate optimization strategies, including graph-based and mathematical programming techniques, to address them.