XPS: EXPL: Exploring the Design Space of Augmented Memory Controllers with Native Support for In-Memory Data Storage

作为全球信息技术基础设施的基石，大规模并行处理平台承载着数量不断增加的实时内存计算应用(例如，数据/图形分析、事务处理、机器学习和商业智能)。因此，大规模分布式内存数据存储成为大规模并行处理平台中非常重要的组成部分。然而，传统的存储器内数据存储的实现往往占用大量的存储器容量并消耗大量的CPU周期。这使得内存中的数据存储在内存和CPU资源方面都要承受巨大的成本开销。如何很好地解决这一成本挑战在很大程度上决定了未来大规模并行处理平台的整体系统性能和效率。该项目将对研究界和行业产生重大影响，同时为研究生和本科生提供跨学科培训，并吸引不同层次和背景的学生广泛参与合作研究和教育。该项目提出通过增强硬件内存控制器的功能和数据处理能力来提高内存数据存储的成本效益。具体地说，内存中的文件系统和内存控制器将跨软件/硬件层明确地协同工作，并分担优化内存中数据存储实现的责任。这种跨层设计框架使得能够使用存储器占用减少技术来降低存储器资源成本，而不会招致CPU开销。此外，存储控制器将集成定制的硬件引擎，这些引擎可以执行某些面向存储的数据处理任务。在实现内存中数据存储时，可以利用内存控制器中的那些定制的存储数据处理引擎来直接降低内存和CPU资源开销。将实现一个基于现场可编程门阵列的平台进行实验，以进一步实证验证所开发的设计方案的可行性和潜在有效性。

As the cornerstone of the global information technology infrastructure, large-scale parallel processing platforms host an ever-increasing amount of real-time in-memory computing applications (e.g., data/graph analytics, transaction processing, machine learning, and business intelligence). As a result, large-scale distributed in-memory data storage has become a very important component in large-scale parallel processing platforms. Nevertheless, conventional realization of in-memory data storage tends to occupy a large amount of memory capacity and consume substantial CPU cycles. This makes in-memory data storage subject to a significant cost overhead in terms of both memory and CPU resources. How well this cost challenge can be addressed largely determines the overall system performance and efficiency of future large-scale parallel processing platforms. This project will have significant impact on the research community and the industry, while providing interdisciplinary training of graduate and undergraduate students, and draw broad participation of students of different levels and backgrounds in collaborative research and education.This project proposes to improve the cost effectiveness of in-memory data storage by enhancing the function and data processing capability of the hardware memory controller. In particular, the in-memory filesystem and memory controller will explicitly cooperate together across the software/hardware layers and share the responsibility for optimizing the implementation of in-memory data storage. Such a cross-layer design framework enables the use of memory footprint reduction techniques to reduce memory resource cost without incurring CPU overhead. Moreover, the memory controller will integrate customized hardware engines that can carry out certain storage-oriented data processing tasks. Those customized storage data processing engines in the memory controller can be leveraged to directly reduce the memory and CPU resources overhead in the realization of in-memory data storage. An FPGA-based platform will be implemented to carry out experiments to further empirically validate the feasibility and potential effectiveness of the developed design solutions.