SaTC: CORE: Small: Collaborative: Hardware Architectures for Post-Quantum Cryptography

这项研究项目为一类后量子安全密码(PQC)算法开发了新的硬件设计和实现。虽然今天用于公钥密码学的算法，如RSA算法，或数字签名，很容易被使用量子计算机的“密码分析”攻破，但PQC算法提供了保护，使其免受此类密码分析的影响，因为它们在量子计算机上是无法破解的。为了了解如何从能量、面积和性能的角度创建最高效的硬件PQC设计，该项目将新算法实现为定制的专用集成电路。这项工作主要集中在PQC算法的硬件设计方面，这在很大程度上还没有被探索过。该项目特别通过发展专业和教育活动，促进硬件安全和集成电路研究人员之间以及更广泛受众之间的发展和思想交流。为了加深对PQC算法的理解，本项目开发了用于评估的基于代码的算法的FPGA实现。开发了新的模块设计，如高斯消去法或使用加性FFT的多项式求值，以创建新的高效硬件基元。通过VLSI设计流程进行设计，以实现集成电路，并对其进行功耗、面积和性能评估。解决了PQC算法所使用的大密钥所需的大存储器的问题，以及将集成电路与其他计算平台相结合以创建用于PQC算法的硬件加速器。该项目可能有助于正在进行的美国和国际算法标准化工作。

This research project develops new hardware designs and implementations for a class of post-quantum secure cryptographic (PQC) algorithms. While today's algorithms used for public key cryptography, e.g. the RSA algorithm, or digital signatures are vulnerable to being broken through "cryptanalysis" using quantum computers, PQC algorithms offer protections from such cryptanalysis as they cannot be broken on a quantum computer. To understand how to create the most efficient hardware PQC designs from energy, area, and performance perspective, this project realizes the new algorithms as custom application specific integrated circuits. This work focuses on hardware design aspect of PQC algorithms that has been largely unexplored. This project especially promotes development and exchange of ideas between hardware security and integrated circuit researchers and among a broader audience through development of professional and educational activities. To advance the understanding of the PQC algorithms, this project develops FPGA implementations of the code-based algorithms for evaluation. Novel designs for modules such as Gaussian Elimination, or polynomial evaluation with Additive FFT are developed, to create new and efficient hardware primitives. The designs are taken through VLSI design flow to realize the integrated circuits that are evaluated for power, area, and performance. Issues of large memories, needed for the large keys used by the PQC algorithms, are addressed as well as incorporation of the integrated circuits with other computing platforms to create hardware accelerators for the PQC algorithms. This project may contribute to the ongoing US and international algorithm standardization efforts.