EAGER: Monolithic Integration of 1000-ch Neural Interface System on a Single Silicon Die

来自感觉皮质和初级运动皮质的大量神经元群体的平行记录揭示了编码到神经信号中的丰富信息，并指导了认知和运动行为恢复的研究。在这样的设备中，信息的质量取决于被记录的神经信号的密度。目前脑机接口的记录密度仍然不足以具有临床意义，需要重大改进以帮助严重残疾患者完全恢复活动或其他受损功能。然而，缺乏技术来适应电极-放大器对之间的大量导线计数，以及植入设备中密封封装的复杂性，给临床应用带来了超过1000个通道的巨大挑战。这一早期概念探索性研究资助(AGER)项目将探索一种通过将整个无线神经系统集成到薄硅衬底中来设计无线神经接口系统的变革性方法，从而为未来的脑机接口研究和临床应用开发可扩展的神经接口系统提供一条途径。这项探索性研究的成功将改变脑机接口开发商采取的设计方法，这种方法涉及使用外部电线进行互连，从而使包装变得复杂，并将对专注于认知和运动行为的研究产生直接影响，这些研究需要直接从大脑皮质提取高密度神经记录，以指导神经假体。它还将通过使用普通半导体制造方法制造设备来显著降低制造成本，这可能会为有需要的患者带来更实惠的神经假体。全植入式神经接口系统的设计包含许多组件的复杂集成，包括：电极阵列、放大器、处理器、无线发射器和电池。每个现有的系统都使用导线馈通来建立组件之间的电气连接，这些连接用外壳/包装绝缘，以防止植入过程中的泄漏。这种方法存在许多局限性：可伸缩性受到可用馈通数量的严重限制，运行时间受电池容量的限制，金属外壳会阻碍无线传输，非金属包装的长期耐用性受到质疑，以及笨重的植入设备使手术过程复杂化，并给患者带来不适/风险。因此，需要开发一种具有大规模记录能力的新型脑机接口，以推进基础脑研究、大规模脑电地形图和脑机接口的临床翻译。该项目的目标是在硅衬底上单片集成1000路神经接口系统。通过消除外部布线并使用集成电路中的亚微米互连连接所有电子互连，将每个组件单片集成到单个硅管芯中，从而实现高密度记录。与传统方法相比，这种方法产生了前所未有的优势，包括设计简单和消除复杂的包装。研究工作包括以下几个方面：(1)柱电极阵列的片上集成，(2)射频平面线圈和电容器的背板集成，以及(3)用于高通量神经记录的低功耗小面积放大器阵列和外围电路的设计。

The parallel recordings from large neuron populations in the sensory cortex and primary motor cortex reveal the rich information encoded into neural signals, and guide research in restoring cognitive and motor behaviors. In such devices, the quality of information relies on the density of neural signals being recorded. The recording density in the current brain-machine interface remains insufficient to be clinically relevant and significant improvements are required to help severely disabled patients to fully regain mobility or other impaired functions. However, the lack of technology to accommodate the massive wire counts between electrode-amplifier pairs and the complexity in the hermetic packaging in implant devices present large challenges in moving forward beyond 1000 channels to be clinically relevant. This Early-concept Grant for Exploratory Research (EAGER) project will investigate a transformative approach to design a wireless neural interface system by integrating the entire wireless neural system into a thin silicon substrate, and, thus, introduce an avenue for developing a scalable neural interface system for future brain-machine interface research and clinical use. The success of this exploratory study will transform the design approach taken by brain-machine interface developers, which involves the use of external wires for interconnections and thus complicates the packaging, and will have an immediate impact in research studies focused on cognitive and motor behaviors that demands the extraction of high density neural recordings directly from the cortex to guide the neural prosthetics. It will also significantly lower the manufacturing cost by fabricating the device using common semiconductor fabrication methods, which may result in more affordable neural prosthetics for patients in need.Fully-implantable neural interface systems are designed with a complex integration of many components including: electrode arrays, amplifiers, processors, wireless transmitters, and a battery. Every existing system uses wire feedthroughs to establish electrical connections between the components, and the connections are insulated with casing/packaging to prevent leakage during implant. This method presents many limitations: the scalability is severely limited by the number of feedthroughs available, the runtime is limited to the battery capacity, the metal casing can impede wireless transmissions, the long-term durability is questionable with non-metallic packaging, and the bulky implant device complicates the surgical procedure and introduces discomfort/risks to patients. Thus, the development of a new brain-machine interface with large-scale recording capability are needed to advance basic brain research, large-scale brain mapping and clinical translations of brain-machine interface. This project aims to monolithically integrate a 1000-ch neural interface system in a silicon substrate. The monolithic integration of every component into a single silicon die enables high-density recordings by eliminating external wires and linking all the electronic interconnections using sub-micron interconnects in integrated circuits. This approach yields unprecedented advantages, compared to the conventional approach, including the design simplicity and the elimination of complex packaging. The study is composed of the following efforts: (1) On-chip integration of the pillar electrode array, (2) Backplane integration of RF planar coils and capacitors, and (3) Design of low-power small footprint amplifier array and peripheral circuitries for high-throughput neural recordings.